Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2019-11-17 | riscv: provide native clint access for M-mode | Christoph Hellwig | 1 | -0/+2 |
2019-11-13 | riscv: add support for MMIO access to the timer registers | Christoph Hellwig | 1 | -1/+2 |
2019-11-13 | riscv: implement remote sfence.i using IPIs | Christoph Hellwig | 1 | -0/+3 |
2019-11-13 | riscv: poison SBI calls for M-mode | Christoph Hellwig | 1 | -2/+3 |
2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner | 1 | -9/+1 |
2019-05-16 | riscv: fix sbi_remote_sfence_vma{,_asid}. | Gary Guo | 1 | -7/+12 |
2017-09-26 | RISC-V: Device, timer, IRQs, and the SBI | Palmer Dabbelt | 1 | -0/+100 |