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2022-06-01riscv: dts: icicle: sort nodes alphabeticallyConor Dooley1-52/+52
The icicle device tree is in a "random" order, so clean it up and sort its elements alphabetically to match the newly added PolarBerry dts. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220509142610.128590-11-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-01riscv: microchip: icicle: readability fixesConor Dooley1-3/+5
Fix the sort order of the status properties, remove some extra whitespace in the mmc entry & add whitespace to the mac entry containing the phys so that the dt is easier to read. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220509142610.128590-10-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-01riscv: dts: microchip: add the sundance polarberryConor Dooley3-0/+116
Add a minimal device tree for the PolarFire SoC based Sundance PolarBerry. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220509142610.128590-9-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-01riscv: dts: microchip: make the fabric dtsi board specificConor Dooley3-1/+3
Currently mpfs-fabric.dtsi is included by mpfs.dtsi - which is fine currently since there is only one board with this SoC upstream. However if another board was added, it would include the fabric contents of the Icicle Kit's reference design. To avoid this, rename mpfs-fabric.dtsi to mpfs-icicle-kit-fabric.dtsi & include it in the dts rather than mpfs.dtsi. mpfs-icicle-kit-fabric.dtsi specifically matches the 22.03 reference design for the icicle kit's FPGA fabric & an older version of the design may not have the i2c or pwm devices - so add the compatible string to document this. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220509142610.128590-6-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-01riscv: dts: microchip: remove soc vendor from filenamesConor Dooley4-3/+3
Having the SoC vendor both as the directory and in the filename adds little. Remove microchip from the filenames so that the files will resemble the other directories in riscv (and arm64). The new names follow a soc-board.dts & soc{,-fabric}.dtsi pattern. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220509142610.128590-4-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-01riscv: dts: microchip: move sysctrlr out of soc busConor Dooley1-5/+5
The MPFS system controller has no registers of its own, so move it out of the soc node to avoid dtbs_check warnings: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: soc: syscontroller: {'compatible': ['microchip,mpfs-sys-controller'], 'mboxes': [[15, 0]], 'status': ['okay']} should not be valid under {'type': 'object'} Reported-by: Palmer Dabbelt <palmer@rivosinc.com> Suggested-by: Rob Herring <robh@kernel.org> Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220509142610.128590-3-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-01riscv: dts: microchip: remove icicle memory clocksConor Dooley1-2/+0
The clock properties in the icicle kit's memory entries cause dtbs_check errors: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: /: memory@80000000: 'clocks' does not match any of the regexes: 'pinctrl-[0-9]+' Get rid of the clocks to avoid the errors. Reported-by: Palmer Dabbelt <palmer@rivosinc.com> Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Fixes: 5b28df37d311 ("riscv: dts: microchip: update peripherals in icicle kit device tree") Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220509142610.128590-2-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-05-31Merge tag 'riscv-for-linus-5.19-mw0' of ↵Linus Torvalds1-1/+2
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for the Svpbmt extension, which allows memory attributes to be encoded in pages - Support for the Allwinner D1's implementation of page-based memory attributes - Support for running rv32 binaries on rv64 systems, via the compat subsystem - Support for kexec_file() - Support for the new generic ticket-based spinlocks, which allows us to also move to qrwlock. These should have already gone in through the asm-geneic tree as well - A handful of cleanups and fixes, include some larger ones around atomics and XIP * tag 'riscv-for-linus-5.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (51 commits) RISC-V: Prepare dropping week attribute from arch_kexec_apply_relocations[_add] riscv: compat: Using seperated vdso_maps for compat_vdso_info RISC-V: Fix the XIP build RISC-V: Split out the XIP fixups into their own file RISC-V: ignore xipImage RISC-V: Avoid empty create_*_mapping definitions riscv: Don't output a bogus mmu-type on a no MMU kernel riscv: atomic: Add custom conditional atomic operation implementation riscv: atomic: Optimize dec_if_positive functions riscv: atomic: Cleanup unnecessary definition RISC-V: Load purgatory in kexec_file RISC-V: Add purgatory RISC-V: Support for kexec_file on panic RISC-V: Add kexec_file support RISC-V: use memcpy for kexec_file mode kexec_file: Fix kexec_file.c build error for riscv platform riscv: compat: Add COMPAT Kbuild skeletal support riscv: compat: ptrace: Add compat_arch_ptrace implement riscv: compat: signal: Add rt_frame implementation riscv: add memory-type errata for T-Head ...
2022-05-20Merge tag 'riscv-for-linus-5.18-rc8' of ↵Linus Torvalds2-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Palmer Dabbelt: - fix the fu540-c000 device tree to avoid a schema check failure on the DMA node name - fix typo in the PolarFire SOC device tree * tag 'riscv-for-linus-5.18-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: dts: microchip: fix gpio1 reg property typo riscv: dts: sifive: fu540-c000: align dma node name with dtschema
2022-05-19riscv: dts: microchip: fix gpio1 reg property typoConor Paxton1-1/+1
Fix reg address typo in the gpio1 stanza. Signed-off-by: Conor Paxton <conor.paxton@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Link: https://lore.kernel.org/r/20220517104058.2004734-1-conor.paxton@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-05-19riscv: dts: sifive: fu540-c000: align dma node name with dtschemaKrzysztof Kozlowski1-1/+1
Fixes dtbs_check warnings like: dma@3000000: $nodename:0: 'dma@3000000' does not match '^dma-controller(@.*)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220407193856.18223-1-krzysztof.kozlowski@linaro.org Fixes: c5ab54e9945b ("riscv: dts: add support for PDMA device of HiFive Unleashed Rev A00") Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-04-22riscv: dts: microchip: reparent mpfs clocksConor Dooley2-5/+5
The 600M clock in the fabric is not the real reference, replace it with a 125M clock which is the correct value for the icicle kit. Rename the msspllclk node to mssrefclk since this is now the input to, not the output of, the msspll clock. Control of the msspll clock has been moved into the clock configurator, so add the register range for it to the clk configurator. Finally, add a new output of the clock config block which will provide the 1M reference clock for the MTIMER and the rtc. Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220413075835.3354193-10-conor.dooley@microchip.com Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-04-22riscv: dts: microchip: fix usage of fic clocks on mpfsConor Dooley2-3/+15
The fic clocks passed to the pcie controller and other peripherals in the device tree are not the clocks they actually run on. The fics are actually clock domain crossers & the clock config blocks output is the mss/cpu side input to the interconnect. The peripherals are actually clocked by fixed frequency clocks embedded in the fpga fabric. Fix the device tree so that these peripherals use the correct clocks. The fabric side FIC0 & FIC1 inputs both use the same 125 MHz, so only one clock is created for them. Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220413075835.3354193-4-conor.dooley@microchip.com Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-04-20riscv: dts: rename the node name of dmaZong Li1-1/+1
Rename the node name by the generic DMA naming Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-04-20riscv: dts: Add dma-channels property and modify compatibleZong Li1-1/+2
Add dma-channels property, then we can determine how many channels there by device tree, in addition, we add the pdma versioning scheme for compatible. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-04-01Merge tag 'riscv-for-linus-5.18-mw1' of ↵Linus Torvalds4-0/+8
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Palmer Dabbelt: "This has a handful of new features: - Support for CURRENT_STACK_POINTER, which enables some extra stack debugging for HARDENED_USERCOPY. - Support for the new SBI CPU idle extension, via cpuidle and suspend drivers. - Profiling has been enabled in the defconfigs. but is mostly fixes and cleanups" * tag 'riscv-for-linus-5.18-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (21 commits) RISC-V: K210 defconfigs: Drop redundant MEMBARRIER=n RISC-V: defconfig: Drop redundant SBI HVC and earlycon Documentation: riscv: remove non-existent directory from table of contents riscv: cpu.c: don't use kernel-doc markers for comments RISC-V: Enable profiling by default RISC-V: module: fix apply_r_riscv_rcv_branch_rela typo RISC-V: Declare per cpu boot data as static RISC-V: Fix a comment typo in riscv_of_parent_hartid() riscv: Increase stack size under KASAN riscv: Fix fill_callchain return value riscv: dts: canaan: Fix SPI3 bus width riscv: Rename "sp_in_global" to "current_stack_pointer" riscv module: remove (NOLOAD) RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine dt-bindings: Add common bindings for ARM and RISC-V idle states cpuidle: Add RISC-V SBI CPU idle driver cpuidle: Factor-out power domain related code from PSCI domain driver RISC-V: Add SBI HSM suspend related defines RISC-V: Add arch functions for non-retentive suspend entry/exit RISC-V: Rename relocate() and make it global ...
2022-03-30riscv: dts: canaan: Fix SPI3 bus widthNiklas Cassel4-0/+8
According to the K210 Standalone SDK Programming guide: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf Section 15.4.3.3: SPI0 and SPI1 supports: standard, dual, quad and octal transfers. SPI3 supports: standard, dual and quad transfers (octal is not supported). In order to support quad transfers (Quad SPI), SPI3 must have four IO wires connected to the SPI flash. Update the device tree to specify the correct bus width. Tested on maix bit, maix dock and maixduino, which all have the same SPI flash (gd25lq128d) connected to SPI3. maix go is untested, but it would not make sense for this k210 board to be designed differently. Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Fixes: 8f5b0e79f3e5 ("riscv: Add SiPeed MAIXDUINO board device tree") Fixes: 8194f08bda18 ("riscv: Add SiPeed MAIX GO board device tree") Fixes: a40f920964c4 ("riscv: Add SiPeed MAIX DOCK board device tree") Fixes: 97c279bcf813 ("riscv: Add SiPeed MAIX BiT board device tree") Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-03-30Merge tag 'clk-for-linus' of ↵Linus Torvalds2-24/+24
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "There's one large change in the core clk framework here. We change how clk_set_rate_range() works so that the frequency is re-evaulated each time the rate is changed. Previously we wouldn't let clk providers see a rate that was different if it was still within the range, which could be bad for power if the clk could run slower when a range expands. Now the clk provider can decide to do something differently when the constraints change. This broke Nvidia's clk driver so we had to wait for the fix for that to bake a little more in -next. The rate range patch series also introduced a kunit suite for the clk framework that we're going to extend in the next release. It already made it easy to find corner cases in the rate range patches so I'm excited to see it cover more clk code and increase our confidence in core framework patches in the future. I also added a kunit test for the basic clk gate code and that work will continue to cover more basic clk types: muxes, dividers, etc. Beyond the core code we have the usual set of clk driver updates and additions. Qualcomm again dominates the diffstat here with lots more SoCs being supported and i.MX follows afer that with a similar number of SoCs gaining clk drivers. Beyond those large additions there's drivers being modernized to use clk_parent_data so we can move away from global string names for all the clks in an SoC. Finally there's lots of little fixes all over the clk drivers for typos, warnings, and missing clks that aren't critical and get batched up waiting for the next merge window to open. Nothing super big stands out in the driver pile. Full details are below. Core: - Make clk_set_rate_range() re-evaluate the limits each time - Introduce various clk_set_rate_range() tests - Add clk_drop_range() to drop a previously set range New Drivers: - i.MXRT1050 clock driver and bindings - i.MX8DXL clock driver and bindings - i.MX93 clock driver and bindings - NCO blocks on Apple SoCs - Audio clks on StarFive JH7100 RISC-V SoC - Add support for the new Renesas RZ/V2L SoC - Qualcomm SDX65 A7 PLL - Qualcomm SM6350 GPU clks - Qualcomm SM6125, SM6350, QCS2290 display clks - Qualcomm MSM8226 multimedia clks Updates: - Kunit tests for clk-gate implementation - Terminate arrays with sentinels and make that clearer - Cleanup SPDX tags - Fix typos in comments - Mark mux table as const in clk-mux - Make the all_lists array const - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add support for dynamic mode - Clock configuration on Microchip PolarFire SoCs - Free allocations on probe error in Mediatek clk driver - Modernize Mediatek clk driver by consolidating code - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on Renesas R-Car S4-8 - Improve the clocks for the Rockchip rk3568 display outputs (parenting, pll-rates) - Use of_device_get_match_data() instead of open-coding on Rockchip rk3568 - Reintroduce the expected fractional-divider behaviour that disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - Remove SYS PLL 1/2 clock gates for i.MX8M* - Remove AUDIO MCLK ROOT from i.MX7D - Add fracn gppll clock type used by i.MX93 - Add new composite clock for i.MX93 - Add missing media mipi phy ref clock for i.MX8MP - Fix off by one in imx_lpcg_parse_clks_from_dt() - Rework for the imx pll14xx - sama7g5: One low priority fix for GCLK of PDMC - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8 - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3 - Add CAN-FD clocks on Renesas R-Car V3U - Qualcomm SC8280XP RPMCC - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to YAML - Convert various Qualcomm drivers to use clk_parent_data - Remove test clocks from various Qualcomm drivers - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs - Better pixel clk frequency support on Qualcomm RCG2 clks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits) clk: zynq: Update the parameters to zynq_clk_register_periph_clk clk: zynq: trivial warning fix clk: Drop the rate range on clk_put() clk: test: Test clk_set_rate_range on orphan mux clk: Initialize orphan req_rate dt-bindings: clock: drop useless consumer example dt-bindings: clock: renesas: Make example 'clocks' parsable clk: qcom: gcc-msm8994: Fix gpll4 width dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml clk: rs9: Add Renesas 9-series PCIe clock generator driver clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index() clk: visconti: prevent array overflow in visconti_clk_register_gates() dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator clk: sifive: Move all stuff into SoCs header files from C files clk: sifive: Add SoCs prefix in each SoCs-dependent data riscv: dts: Change the macro name of prci in each device node dt-bindings: change the macro name of prci in header files and example clk: sifive: duplicate the macro definitions for the time being clk: qcom: sm6125-gcc: fix typos in comments clk: ti: clkctrl: fix typos in comments ...
2022-03-25Merge tag 'riscv-for-linus-5.18-mw0' of ↵Linus Torvalds3-66/+328
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for Sv57-based virtual memory. - Various improvements for the MicroChip PolarFire SOC and the associated Icicle dev board, which should allow upstream kernels to boot without any additional modifications. - An improved memmove() implementation. - Support for the new Ssconfpmf and SBI PMU extensions, which allows for a much more useful perf implementation on RISC-V systems. - Support for restartable sequences. * tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (36 commits) rseq/selftests: Add support for RISC-V RISC-V: Add support for restartable sequence MAINTAINERS: Add entry for RISC-V PMU drivers Documentation: riscv: Remove the old documentation RISC-V: Add sscofpmf extension support RISC-V: Add perf platform driver based on SBI PMU extension RISC-V: Add RISC-V SBI PMU extension definitions RISC-V: Add a simple platform driver for RISC-V legacy perf RISC-V: Add a perf core library for pmu drivers RISC-V: Add CSR encodings for all HPMCOUNTERS RISC-V: Remove the current perf implementation RISC-V: Improve /proc/cpuinfo output for ISA extensions RISC-V: Do no continue isa string parsing without correct XLEN RISC-V: Implement multi-letter ISA extension probing framework RISC-V: Extract multi-letter extension names from "riscv, isa" RISC-V: Minimal parser for "riscv, isa" strings RISC-V: Correctly print supported extensions riscv: Fixed misaligned memory access. Fixed pointer comparison. MAINTAINERS: update riscv/microchip entry riscv: dts: microchip: add new peripherals to icicle kit device tree ...
2022-03-15riscv: dts: Change the macro name of prci in each device nodeZong Li2-24/+24
We currently change the macro name for fu540 and fu740 by adding the prefix respectively, these marcos are referenced by some device nodes, they should be modified as well. Signed-off-by: Zong Li <zong.li@sifive.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/db92d209fa700f7da8bc8028083476fcc138d80e.1646388139.git.zong.li@sifive.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-09riscv: dts: microchip: add new peripherals to icicle kit device treeConor Dooley2-0/+213
Add new peripherals to the MPFS, and enable them in the Icicle kit device tree: 2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller, USB host & system controller. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-03-09riscv: dts: microchip: update peripherals in icicle kit device treeConor Dooley2-17/+29
Assorted minor changes to the MPFS/Icicle kit device tree: - enable mmuart4 instead of mmuart0 - remove sifive pdma - split memory node to match updated fpga design - move stdout path to serial1 to avoid collision with bootloader running on the e51 Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-03-09riscv: dts: microchip: refactor icicle kit device treeConor Dooley2-50/+52
Assorted minor changes to the MPFS/Icicle kit device tree: - rename serial to mmuart to match microchip documentation - move phy0 inside mac1 node to match phy configuration - add labels where missing (cpus, cache controller) - add missing address cells & interrupts to MACs Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-03-09riscv: dts: microchip: add fpga fabric section to icicle kitConor Dooley3-0/+34
Split the device tree for the Microchip MPFS into two sections by adding microchip-mpfs-fabric.dtsi, which contains peripherals contained in the FPGA fabric. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-03-09riscv: dts: microchip: use clk defines for icicle kitConor Dooley2-13/+14
Update the Microchip Icicle kit device tree by replacing clock related magic numbers with their defined counterparts. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-03-03riscv: dts: k210: fix broken IRQs on hart1Niklas Cassel1-1/+2
Commit 67d96729a9e7 ("riscv: Update Canaan Kendryte K210 device tree") incorrectly removed two entries from the PLIC interrupt-controller node's interrupts-extended property. The PLIC driver cannot know the mapping between hart contexts and hart ids, so this information has to be provided by device tree, as specified by the PLIC device tree binding. The PLIC driver uses the interrupts-extended property, and initializes the hart context registers in the exact same order as provided by the interrupts-extended property. In other words, if we don't specify the S-mode interrupts, the PLIC driver will simply initialize the hart0 S-mode hart context with the hart1 M-mode configuration. It is therefore essential to specify the S-mode IRQs even though the system itself will only ever be running in M-mode. Re-add the S-mode interrupts, so that we get working IRQs on hart1 again. Cc: <stable@vger.kernel.org> Fixes: 67d96729a9e7 ("riscv: Update Canaan Kendryte K210 device tree") Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-20riscv: dts: sifive unmatched: Add gpio poweroffRon Economos1-0/+5
Some of the GPIO pins on the Unmatched are wire up to control the power of the board, indicate that in the device tree. Signed-off-by: Ron Economos <w6rz@comcast.net> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-19Merge tag 'riscv-for-linus-5.17-mw0' of ↵Linus Torvalds9-77/+72
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for the DA9063 as used on the HiFive Unmatched. - Support for relative extables, which puts us in line with other architectures and save some space in vmlinux. - A handful of kexec fixes/improvements, including the ability to run crash kernels from PCI-addressable memory on the HiFive Unmatched. - Support for the SBI SRST extension, which allows systems that do not have an explicit driver in Linux to reboot. - A handful of fixes and cleanups, including to the defconfigs and device trees. * tag 'riscv-for-linus-5.17-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (52 commits) RISC-V: Use SBI SRST extension when available riscv: mm: fix wrong phys_ram_base value for RV64 RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=n riscv: head: remove useless __PAGE_ALIGNED_BSS and .balign riscv: errata: alternative: mark vendor_patch_func __initdata riscv: head: make secondary_start_common() static riscv: remove cpu_stop() riscv: try to allocate crashkern region from 32bit addressible memory riscv: use hart id instead of cpu id on machine_kexec riscv: Don't use va_pa_offset on kdump riscv: dts: sifive: fu540-c000: Fix PLIC node riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values riscv: dts: sifive: Group tuples in register properties riscv: dts: sifive: Group tuples in interrupt properties riscv: dts: microchip: mpfs: Group tuples in interrupt properties riscv: dts: microchip: mpfs: Fix clock controller node riscv: dts: microchip: mpfs: Fix reference clock node riscv: dts: microchip: mpfs: Fix PLIC node riscv: dts: microchip: mpfs: Drop empty chosen node riscv: dts: canaan: Group tuples in interrupt properties ...
2022-01-19Merge tag 'kbuild-v5.17' of ↵Linus Torvalds1-3/+1
git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild Pull Kbuild updates from Masahiro Yamada: - Add new kconfig target 'make mod2noconfig', which will be useful to speed up the build and test iteration. - Raise the minimum supported version of LLVM to 11.0.0 - Refactor certs/Makefile - Change the format of include/config/auto.conf to stop double-quoting string type CONFIG options. - Fix ARCH=sh builds in dash - Separate compression macros for general purposes (cmd_bzip2 etc.) and the ones for decompressors (cmd_bzip2_with_size etc.) - Misc Makefile cleanups * tag 'kbuild-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild: (34 commits) kbuild: add cmd_file_size arch: decompressor: remove useless vmlinux.bin.all-y kbuild: rename cmd_{bzip2,lzma,lzo,lz4,xzkern,zstd22} kbuild: drop $(size_append) from cmd_zstd sh: rename suffix-y to suffix_y doc: kbuild: fix default in `imply` table microblaze: use built-in function to get CPU_{MAJOR,MINOR,REV} certs: move scripts/extract-cert to certs/ kbuild: do not quote string values in include/config/auto.conf kbuild: do not include include/config/auto.conf from shell scripts certs: simplify $(srctree)/ handling and remove config_filename macro kbuild: stop using config_filename in scripts/Makefile.modsign certs: remove misleading comments about GCC PR certs: refactor file cleaning certs: remove unneeded -I$(srctree) option for system_certificates.o certs: unify duplicated cmd_extract_certs and improve the log certs: use $< and $@ to simplify the key generation rule kbuild: remove headers_check stub kbuild: move headers_check.pl to usr/include/ certs: use if_changed to re-generate the key when the key type is changed ...
2022-01-10Merge tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds4-0/+397
Pull RISC-V SoC updates from Arnd Bergmann: "Add support for StarFive JH7100 RISC-V SoC This adds support for the StarFive JH7100, including the necessary device drivers and DT files for the BeagleV Starlight prototype board, with additional boards to be added later. This SoC promises to be the first usable low-cost platform for RISC-V. I've taken this through the SoC tree in the anticipation of adding a few other Arm based SoCs as well, but those did not pass the review in time, so it's only this one" * tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: reset: starfive-jh7100: Fix 32bit compilation RISC-V: Add BeagleV Starlight Beta device tree RISC-V: Add initial StarFive JH7100 device tree serial: 8250_dw: Add StarFive JH7100 quirk dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts pinctrl: starfive: Add pinctrl driver for StarFive SoCs dt-bindings: pinctrl: Add StarFive JH7100 bindings dt-bindings: pinctrl: Add StarFive pinctrl definitions reset: starfive-jh7100: Add StarFive JH7100 reset driver dt-bindings: reset: Add Starfive JH7100 reset bindings dt-bindings: reset: Add StarFive JH7100 reset definitions clk: starfive: Add JH7100 clock generator driver dt-bindings: clock: starfive: Add JH7100 bindings dt-bindings: clock: starfive: Add JH7100 clock definitions dt-bindings: interrupt-controller: Add StarFive JH7100 plic dt-bindings: timer: Add StarFive JH7100 clint RISC-V: Add StarFive SoC Kconfig option
2022-01-09riscv: dts: sifive: fu540-c000: Fix PLIC nodeGeert Uytterhoeven1-2/+3
Fix the device node for the Platform-Level Interrupt Controller (PLIC): - Add missing "#address-cells" property, - Sort properties according to DT bindings. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible valuesGeert Uytterhoeven1-1/+1
"make dtbs_check": arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: $nodename:0: '/' was expected From schema: Documentation/devicetree/bindings/riscv/sifive.yaml arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: compatible: 'oneOf' conditional failed, one must be fixed: 'sifive,fu540-c000' is not one of ['sifive,hifive-unleashed-a00'] 'sifive,fu540-c000' is not one of ['sifive,hifive-unmatched-a00'] 'sifive,fu540-c000' was expected 'sifive,fu740-c000' was expected 'sifive,fu540' was expected 'sifive,fu740' was expected From schema: Documentation/devicetree/bindings/riscv/sifive.yaml This happens because the "soc" subnode declares compatibility with "sifive,fu540-c000" and "sifive,fu540", while these are only intended for the root node. Fix this by removing the bogus compatible values from the "soc" node. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09riscv: dts: sifive: Group tuples in register propertiesGeert Uytterhoeven1-6/+6
To improve human readability and enable automatic validation, the tuples in "reg" properties containing register blocks should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09riscv: dts: sifive: Group tuples in interrupt propertiesGeert Uytterhoeven2-17/+18
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09riscv: dts: microchip: mpfs: Group tuples in interrupt propertiesGeert Uytterhoeven1-15/+16
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09riscv: dts: microchip: mpfs: Fix clock controller nodeGeert Uytterhoeven1-9/+0
Fix the device node for the clock controller: - Remove bogus "reg-names" property, - Remove unneeded "clock-output-names" property. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09riscv: dts: microchip: mpfs: Fix reference clock nodeGeert Uytterhoeven2-7/+9
"make dtbs_check" reports: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'} From schema: dtschema/schemas/simple-bus.yaml Fix this by moving the node out of the "soc" subnode. While at it, rename it to "msspllclk", and drop the now superfluous "clock-output-names" property. Move the actual clock-frequency value to the board DTS, since it is not set until bitstream programming time. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09riscv: dts: microchip: mpfs: Fix PLIC nodeGeert Uytterhoeven1-2/+3
Fix the device node for the Platform-Level Interrupt Controller (PLIC): - Add missing "#address-cells" property, - Sort properties according to DT bindings. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09riscv: dts: microchip: mpfs: Drop empty chosen nodeGeert Uytterhoeven1-3/+0
It does not make sense to have an (empty) chosen node in an SoC-specific .dtsi, as chosen is meant for system-specific configuration. It is already provided in microchip-mpfs-icicle-kit.dts anyway. Fixes: 0fa6107eca4186ad ("RISC-V: Initial DTS for Microchip ICICLE board") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09riscv: dts: canaan: Group tuples in interrupt propertiesGeert Uytterhoeven1-11/+12
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Tested-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09riscv: dts: canaan: Fix SPI FLASH node namesGeert Uytterhoeven4-4/+4
"make dtbs_check": arch/riscv/boot/dts/canaan/sipeed_maix_bit.dt.yaml: spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$' From schema: Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml Fix this by renaming all SPI FLASH nodes to "flash". Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Tested-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-08kbuild: do not quote string values in include/config/auto.confMasahiro Yamada1-3/+1
The previous commit fixed up all shell scripts to not include include/config/auto.conf. Now that include/config/auto.conf is only included by Makefiles, we can change it into a more Make-friendly form. Previously, Kconfig output string values enclosed with double-quotes (both in the .config and include/config/auto.conf): CONFIG_X="foo bar" Unlike shell, Make handles double-quotes (and single-quotes as well) verbatim. We must rip them off when used. There are some patterns: [1] $(patsubst "%",%,$(CONFIG_X)) [2] $(CONFIG_X:"%"=%) [3] $(subst ",,$(CONFIG_X)) [4] $(shell echo $(CONFIG_X)) These are not only ugly, but also fragile. [1] and [2] do not work if the value contains spaces, like CONFIG_X=" foo bar " [3] does not work correctly if the value contains double-quotes like CONFIG_X="foo\"bar" [4] seems to work better, but has a cost of forking a process. Anyway, quoted strings were always PITA for our Makefiles. This commit changes Kconfig to stop quoting in include/config/auto.conf. These are the string type symbols referenced in Makefiles or scripts: ACPI_CUSTOM_DSDT_FILE ARC_BUILTIN_DTB_NAME ARC_TUNE_MCPU BUILTIN_DTB_SOURCE CC_IMPLICIT_FALLTHROUGH CC_VERSION_TEXT CFG80211_EXTRA_REGDB_KEYDIR EXTRA_FIRMWARE EXTRA_FIRMWARE_DIR EXTRA_TARGETS H8300_BUILTIN_DTB INITRAMFS_SOURCE LOCALVERSION MODULE_SIG_HASH MODULE_SIG_KEY NDS32_BUILTIN_DTB NIOS2_DTB_SOURCE OPENRISC_BUILTIN_DTB SOC_CANAAN_K210_DTB_SOURCE SYSTEM_BLACKLIST_HASH_LIST SYSTEM_REVOCATION_KEYS SYSTEM_TRUSTED_KEYS TARGET_CPU UNUSED_KSYMS_WHITELIST XILINX_MICROBLAZE0_FAMILY XILINX_MICROBLAZE0_HW_VER XTENSA_VARIANT_NAME I checked them one by one, and fixed up the code where necessary. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2021-12-16riscv: dts: sifive unmatched: Link the tmp451 with its power supplyVincent Pelletier1-0/+1
Fixes the following probe warning: lm90 0-004c: Looking up vcc-supply from device tree lm90 0-004c: Looking up vcc-supply property in node /soc/i2c@10030000/temperature-sensor@4c failed lm90 0-004c: supply vcc not found, using dummy regulator Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2021-12-16riscv: dts: sifive unmatched: Fix regulator for board rev3Vincent Pelletier1-60/+24
The existing values are rejected by the da9063 regulator driver, as they are unachievable with the declared chip setup (non-merged vcore and bmem are unable to provide the declared curent). Fix voltages to match rev3 schematics, which also matches their boot-up configuration within the chip's available precision. Declare bcore1/bcore2 and bmem/bio as merged. Set ldo09 and ldo10 as always-on as their consumers are not declared but exist. Drop ldo current limits as there is no current limit feature for these regulators in the DA9063. Fixes warnings like: DA9063_LDO3: Operation of current configuration missing Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2021-12-16riscv: dts: sifive unmatched: Expose the PMIC sub-functionsVincent Pelletier1-0/+12
These sub-functions are available in the chip revision on this board, so expose them. Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2021-12-16riscv: dts: sifive unmatched: Expose the board ID eepromVincent Pelletier1-0/+10
Mark it as read-only as it is factory-programmed with identifying information, and no executable nor configuration: - eth MAC address - board model (PCB version, BoM version) - board serial number Accidental modification would cause misidentification which could brick the board, so marking read-only seem like both a safe and non-constraining choice. Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2021-12-16riscv: dts: sifive unmatched: Name gpio linesVincent Pelletier1-0/+4
Follow the pin descriptions given in the version 3 of the board schematics. Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2021-12-16RISC-V: Add BeagleV Starlight Beta device treeEmil Renner Berthing3-0/+167
Add initial device tree for the BeagleV Starlight Beta board. About 300 of these boards were sent out as part of a now cancelled BeagleBoard.org project. I2C timing data is based on the device tree in the vendor u-boot port. Heartbeat LED added by Geert. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Co-developed-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-16RISC-V: Add initial StarFive JH7100 device treeEmil Renner Berthing1-0/+230
Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. The CPU and cache data is based on the device tree in the vendor u-boot port. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-11-24riscv: dts: unmatched: Add gpio card detect to mmc-spi-slotBin Meng1-0/+2
Per HiFive Unmatched schematics, the card detect signal of the micro SD card is connected to gpio pin #15, which should be reflected in the DT via the <gpios> property, as described in Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt. [1] https://sifive.cdn.prismic.io/sifive/6a06d6c0-6e66-49b5-8e9e-e68ce76f4192_hifive-unmatched-schematics-v3.pdf Signed-off-by: Bin Meng <bin.meng@windriver.com> Fixes: d573b5558abb ("riscv: dts: add initial board data for the SiFive HiFive Unmatched") Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-03-18 22:25:37 +0000