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2012-07-23powerpc/mpic: Create a revmap with enough entries for IPIs and timersBenjamin Herrenschmidt1-1/+1
The current mpic code creates a linear revmap just big enough for all the sources, which happens to miss the IPIs and timers on some machines. This will in turn break when the irqdomain code loses the fallback of doing a linear search when the revmap fails (and really slows down IPIs otherwise). This happens for example on the U4 based Apple machines such as the dual core PowerMac G5s. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-23Remove stale .rej fileBenjamin Herrenschmidt1-22/+0
Commit 9778b696a0188ad3b3524b383953ee73b31b7b68 accidentally added a .rej file (probably my fault), remove it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-23switch dentry_open() to struct path, make it grab references itselfAl Viro1-10/+8
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2012-07-23spufs: shift dget/mntget towards dentry_open()Al Viro1-28/+18
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2012-07-22Merge branch 'smp-hotplug-for-linus' of ↵Linus Torvalds1-2/+0
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull smp/hotplug changes from Ingo Molnar: "Various cleanups to the SMP hotplug code - a continuing effort of Thomas et al" * 'smp-hotplug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: smpboot: Remove leftover declaration smp: Remove num_booting_cpus() smp: Remove ipi_call_lock[_irq]()/ipi_call_unlock[_irq]() POWERPC: Smp: remove call to ipi_call_lock()/ipi_call_unlock() SPARC: SMP: Remove call to ipi_call_lock_irq()/ipi_call_unlock_irq() ia64: SMP: Remove call to ipi_call_lock_irq()/ipi_call_unlock_irq() x86-smp-remove-call-to-ipi_call_lock-ipi_call_unlock tile: SMP: Remove call to ipi_call_lock()/ipi_call_unlock() S390: Smp: remove call to ipi_call_lock()/ipi_call_unlock() parisc: Smp: remove call to ipi_call_lock()/ipi_call_unlock() mn10300: SMP: Remove call to ipi_call_lock()/ipi_call_unlock() hexagon: SMP: Remove call to ipi_call_lock()/ipi_call_unlock()
2012-07-13powerpc/iommu: Fix iommu pool initializationBenjamin Herrenschmidt1-2/+2
The iommu pool patch has a bug where it would cause a crash when using only one pool (based on the size of the DMA window). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-13Merge remote-tracking branch 'kumar/next' into nextBenjamin Herrenschmidt56-1674/+1601
Freescale updates for 3.6
2012-07-13powerpc/eeh: Check handle_eeh_events() return valueKleber Sacilotto de Souza1-2/+4
Function eeh_event_handler() dereferences the pointer returned by handle_eeh_events() without checking, causing a crash if NULL was returned, which is expected in some situations. This patch fixes this bug by checking for the value returned by handle_eeh_events() before dereferencing it. Signed-off-by: Kleber Sacilotto de Souza <klebers@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: stable@vger.kernel.org [v3.4+]
2012-07-12powerpc/85xx: Add phy nodes in SGMII mode for MPC8536/44/72DS & P2020DSJia Hongtao4-0/+44
In SGMII riser card different PHY chip are used with different external IRQ from eTSEC. To support PHY link state auto detect in SGMII mode we should add another group of PHY nodes for SGMII mode. For MPC8572DS IRQ6 is used for PHY0~PHY1, IRQ7 is used for PHY2~PHY3. For MPC8544DS and MPC8536DS IRQ6 is used for PHY0~PHY1. For P2020DS IRQ5 is used for PHY1~PHY2. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-11Merge branch 'for-upstream-master' of git://github.com/agraf/linux-2.6Avi Kivity1-0/+1
PPC fix from Alex Graf: "It contains an important bug fix which can lead to guest freezes when using PAPR guests with PR KVM." * 'for-upstream-master' of git://github.com/agraf/linux-2.6: powerpc/kvm: Fix "PR" KVM implementation of H_CEDE Signed-off-by: Avi Kivity <avi@redhat.com>
2012-07-11KVM: PPC: Critical interrupt emulation supportBharat Bhushan1-0/+25
rfci instruction and CSRR0/1 registers are emulated. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-07-11KVM: PPC: e500mc: Fix tlbilx emulation for 64-bit guestsMihai Caraman1-1/+2
tlbilxva emulation was using an u32 variable for guest effective address. Replace it with gva_t type to handle 64-bit guests. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-07-11KVM: PPC64: booke: Set interrupt computation mode for 64-bit hostMihai Caraman1-1/+4
64-bit host needs to remain in 64-bit mode when an exception take place. Set interrupt computaion mode in EPCR register. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-07-11KVM: PPC: bookehv: Add ESR flag to Data Storage InterruptMihai Caraman1-1/+1
ESR register is required by Data Storage Interrupt handling code. Add the specific flag to the interrupt handler. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-07-11KVM: PPC: bookehv64: Add support for std/ld emulation.Varun Sethi1-0/+16
Add support for std/ld emulation. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-07-11booke: Added crit/mc exception handler for e500v2Bharat Bhushan1-28/+27
Watchdog is taken at critical exception level. So this patch is tested with host watchdog exception happening when guest is running. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-07-11booke/bookehv: Add host crit-watchdog exception supportBharat Bhushan2-0/+23
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-07-11powerpc/kvm: Fix "PR" KVM implementation of H_CEDEBenjamin Herrenschmidt1-0/+1
H_CEDE should enable the vcpu's MSR:EE bit. It does on "HV" KVM (it's burried in the assembly code though) and as far as I can tell, qemu does it as well. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-07-11irqdomain: Eliminate dedicated radix lookup functionsGrant Likely2-2/+2
In preparation to remove the slow revmap path, eliminate the public radix revmap lookup functions. This simplifies the code and makes the slowpath removal patch a lot simpler. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com>
2012-07-11irqdomain: Always update revmap when setting up a virqGrant Likely1-3/+0
At irq_setup_virq() time all of the data needed to update the reverse map is available, but the current code ignores it and relies upon the slow path to insert revmap records. This patch adds revmap updating to the setup path so the slow path will no longer be necessary. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com>
2012-07-11Merge tag 'v3.5-rc6' into irqdomain/nextGrant Likely12-150/+132
Linux 3.5-rc6
2012-07-11powerpc/e500: add paravirt QEMU platformScott Wood4-0/+93
This gives the kernel a paravirtualized machine to target, without requiring both sides to pretend to be targeting a specific board that likely has little to do with the host in KVM scenarios. This avoids the need to add new boards to QEMU just to be able to run KVM on new CPUs. As this is the first platform that can run with either e500v2 or e500mc, CONFIG_PPC_E500MC is now a legitimately user configurable option, so add a help text. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-11powerpc/mpc85xx_ds: convert to unified PCI initScott Wood1-68/+29
Similar to how the primary PCI bridge is identified by looking for an isa subnode, we determine whether to apply uli exclusions by looking for a uli subnode. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-11powerpc/fsl-pci: get PCI init out of board filesScott Wood2-1/+78
As an alternative incremental starting point to Jia Hongtao's patchset, get the FSL PCI init out of the board files, but do not yet convert to a platform driver. Rather than having each board supply a magic register offset for determining the "primary" bus, we look for which PCI host bridge contains an ISA node within its subtree. If there is no ISA node, normally that would mean there is no primary bus, but until certain bugs are fixed we arbitrarily designate a primary in this case. Conversion to a platform driver and related improvements can happen after this, as the ordering issues are sorted out. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-11powerpc/85xx: Update corenet64_smp_defconfigShengzhou Liu1-14/+51
Enable USB, MMC, SATA, LBC, MTD, NAND, SPI, PCIe, EDAC, VFAT, NFS, etc. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-11powerpc/85xx: Update corenet32_smp_defconfigShengzhou Liu1-0/+8
- Enable NAND support - Enable CONFIG_PCI_MSI and CONFIG_MMC_SDHCI_OF Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-11powerpc/85xx: Rename P1021RDB-PC device trees to be consistentXu Jiucheng3-5/+5
The board is really P1021RDB-PC, so rename from p1021rdb.* to p1021rdb-pc.* Signed-off-by: Xu Jiucheng <Jiucheng.Xu@freescale.com> Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-11powerpc/watchdog: move booke watchdog param related code to setup-common.cShaohui Xie2-24/+27
Currently, BOOKE watchdog code for checking "wdt" and "wdt_period" is in setup_32.c, it cannot be used in 64-bit, so move it to a common place setup-common.c, which will be shared by 32-bit and 64-bit. Also, replace the simple_strtoul with kstrtol. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-11powerpc: Disable /dev/port interface on systems without an ISA bridgeHaren Myneni1-0/+8
Some power systems do not have legacy ISA devices. So, /dev/port is not a valid interface on these systems. User level tools such as kbdrate is trying to access the device using this interface which is causing the system crash. This patch will fix this issue by not creating this interface on these powerpc systems. Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-11of: Improve prom_update_property() functionDong Aisheng3-24/+8
prom_update_property() currently fails if the property doesn't actually exist yet which isn't what we want. Change to add-or-update instead of update-only, then we can remove a lot duplicated lines. Suggested-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-11powerpc: Add "memory" attribute for mfmsr()Tiejun Chen1-1/+2
Add "memory" attribute in inline assembly language as a compiler barrier to make sure 4.6.x GCC don't reorder mfmsr(). Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: stable@vger.kernel.org
2012-07-11powerpc/ftrace: Fix assembly trampoline register usageroger blofeld1-6/+6
Just like the module loader, ftrace needs to be updated to use r12 instead of r11 with newer gcc's. Signed-off-by: Roger Blofeld <blofeldus@yahoo.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: stable@vger.kernel.org
2012-07-11powerpc/hw_breakpoints: Fix incorrect pointer accessNaveen N. Rao1-1/+1
If arch_validate_hwbkpt_settings() fails, bp->ctx won't be valid and the kernel panics. Add a check to fix this. Reported-by: Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-11powerpc: Put the gpr save/restore functions in their own sectionStephen Rothwell1-1/+4
This allows the linker to know that calls to them do not need to switch TOC and stop errors like the following when linking large configurations: powerpc64-linux-ld: drivers/built-in.o: In function `.gpiochip_is_requested': (.text+0x4): sibling call optimization to `_savegpr0_29' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `_savegpr0_29' extern Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-11powerpc: Add VDSO version of getcpuAnton Blanchard13-4/+140
We have a request for a fast method of getting CPU and NUMA node IDs from userspace. This patch implements a getcpu VDSO function, similar to x86. Ben suggested we use SPRG3 which is userspace readable. SPRG3 can be modified by a KVM guest, so we save the SPRG3 value in the paca and restore it when transitioning from the guest to the host. I have a glibc patch that implements sched_getcpu on top of this. Testing on a POWER7: baseline: 538 cycles vdso: 30 cycles Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-11powerpc: Add a symbol for hypervisor trampolinesMichael Ellerman1-0/+1
Purely for cosmetic purposes, otherwise it can appear that we are in single_step_pSeries() which is slightly confusing. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-11powerpc/cpuidle: Fixes for pseries_idle hotplug notifierDeepthi Dharwar1-5/+18
Currently the call to pseries_notify_cpuidle_add_cpu(), that takes action on the cpuidle front when a cpu is added/removed is being made from smp_xics_setup_cpu(). This caused lockdep issues as reported https://lkml.org/lkml/2012/5/17/2 On addition of each cpu, resources were cleared and re-allocated each time, all in critical section as part of start_secondary() call were interrupts are disabled. To resolve this issue, the pseries_notify_cpuidle_add_cpu() call is is being replaced by a hotplug notifier which would prevent cpuidle resources from being released and allocated each time cpu is onlined in the critical code path. It was fixed in https://lkml.org/lkml/2012/5/18/174. Also it is essential to call cpuidle_enable/disable_device between cpuidle_pause_and_lock() and cpuidle_resume_and_unlock() when used externally to avoid race conditions. Add support for CPU_ONLINE_FROZEN and CPU_DEAD_FROZEN as part of hotplug notify event for pseries_idle and unregister hotplug notifier while exiting out. The above mentioned issues are fixed as part of this patch. Signed-off-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-11powerpc: Fixup oddity in entry_32.SBenjamin Herrenschmidt1-6/+0
When I "fixed" the CONFIG_TRACE_IRQFLAGS case on interrupt entry, I screwed up a little bit with the test for user space vs. kernel. The code is fine, there's just some dead code around it. I basically removed the test and always create the added stack frame whether coming from user or kernel since in any case we do need to save a bunch of volatile registers or bad things would happen (we can take page faults in the kernel for example). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-11powerpc: Use CURRENT_THREAD_INFO instead of open coded assemblyStuart Yoder16-41/+65
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10powerpc/85xx: Add ucc uart support for p1025rdbZhicheng Fan2-1/+55
Add device tree nodes to enable ucc uart support on P1025RDB. Signed-off-by: Zhicheng Fan <B32736@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10powerpc: select PPC_CLOCK unconditionally for FSL_SOCShawn Guo1-1/+1
Freescale PowerPC SoCs share a number of IP blocks with Freescale ARM/IMX SoCs, FlexCAN, SSI, FEC, eSDHC, USB, etc. There are some effort consolidating those drivers to make them work for both architectures. One outstanding difference between two architectures is ARM/IMX will turn off module clocks during platform initialization for power saving and expects drivers manage clocks using clk API, while PowerPC mostly does not do that, and thus does not always build in clk API. Listing all those driver Kconfig options in "select PPC_CLOCK if" seems not scalable for long term maintenance, and could easily introduce Kconfig recursive dependency. This patch chooses to select PPC_CLOCK unconditionally for FSL_SOC to always build clk API for PowerPC in. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10powerpc/qe: set IReady in QE Microcode UploadKokoris, Ioannis3-1/+7
QE Microcode Initialization using qe_upload_microcode() does not work on P1021 if the IRAM-Ready register is not set after the microcode upload. Add a definition for the "I-RAM Ready" register and sets it upon microcode upload completion. Signed-off-by: Ioannis Kokkoris <ioannis.kokoris@siemens-enterprise.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10powerpc/85xx: MPC8572DS - Update the MSI interrupts into 4-cell formatJia Hongtao2-8/+8
With 2-cell format interrupts of MSI PCIe ethernet card can not work. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10powerpc/85xx: MPC8572DS - Fix eTSEC is not available on core1 of AMP bootJia Hongtao1-3/+0
The issue log on core1 is: root@mpc8572ds:~# ifconfig eth0 10.192.208.244 net eth0: could not attach to PHY SIOCSIFFLAGS: No such device To attach PHY node mdio@24520 should not be disabled in dts of core1. Because all PHYs are controlled through this node as follows: mdio@24520 { phy0: ethernet-phy@0 { interrupts = <10 1 0 0>; reg = <0x0>; }; phy1: ethernet-phy@1 { interrupts = <10 1 0 0>; reg = <0x1>; }; phy2: ethernet-phy@2 { interrupts = <10 1 0 0>; reg = <0x2>; }; phy3: ethernet-phy@3 { interrupts = <10 1 0 0>; reg = <0x3>; }; tbi0: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10powerpc/mpic: Use the MPIC_LARGE_VECTORS flag for FSL MPIC.Varun Sethi1-1/+1
We should use the MPIC_LARG_VECTORS flag while intializing the MPIC. This prevents us from eating in to hardware vector number space (MSIs) while setting up internal sources. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10powerpc/e500: make load_up_spe a normal fuctionLiu Yu1-17/+6
So that we can call it when improving SPE switch like book3e did for fp switch. Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10powerpc/85xx: Add BSC9131 RDB SupportPrabhakar Kushwaha7-0/+505
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. The BSC9131 is integrated SoC that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. BSC9131RDB Overview ---------------------- BSC9131 SoC 1Gbyte DDR3 (on board DDR) 128Mbyte 2K page size NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory USB-ULPI eTSEC1: Connected to RGMII PHY eTSEC2: Connected to RGMII PHY DUART interface: supports one UARTs up to 115200 bps for console display Linux runs on e500v2 core and access some DSP peripherals like AIC Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10Revert "powerpc/p3060qds: Add support for P3060QDS board"Timur Tabi7-760/+0
This reverts commit 96cc017c5b7ec095ef047d3c1952b6b6bbf98943. The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10powerpc/85xx: use the BRx registers to enable indirect mode on the P1022DSTimur Tabi2-29/+93
In order to enable the DIU video controller on the P1022DS, the FPGA needs to be switched to "indirect mode", where the localbus is disabled and the FPGA is accessed via writes to localbus chip select signals CS0 and CS1. To obtain the address of CS0 and CS1, the platform driver uses an "indirect pixis mode" device tree node. This node assumes that the localbus 'ranges' property is sorted in chip-select order. That is, reg value 0 maps to CS0, reg value 1 maps to CS1, etc. This is how the 'ranges' property is supposed to be arranged. Unfortunately, the 'ranges' property is often mis-arranged, and not just on the P1022DS. Linux normally does not care, since it does not program the localbus. But the indirect-mode code on the P1022DS does care. The "proper" fix is to have U-Boot fix the 'ranges' property, but this would be too cumbersome. The names and 'reg' properties of all the localbus devices would also need to be updated, and determining which localbus device maps to which chip select is board-specific. Instead, we determine the CS0/CS1 base addresses the same way that U-boot does -- by reading the BRx registers directly and mapping them to physical addresses. This code is simpler and more reliable, and it does not require a U-boot or device tree change. Since the indirect pixis device tree node is no longer needed, the node is deleted from the DTS. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10powerpc/p2041rdb: add NAND node in device treeShaohui Xie1-1/+40
NAND on p2041 uses CS1 as chip select. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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