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path: root/arch/powerpc/platforms/cell/pervasive.c
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2006-12-04[POWERPC] cell: hard disable interrupts in power_save()Benjamin Herrenschmidt1-0/+9
With soft-disabled interrupts in power_save, we can still get external exceptions on Cell, even if we are in pause(0) a.k.a. sleep state. When the CPU really wakes up through the 0x100 (system reset) vector, while we have already started processing the 0x500 (external) exception, we get a panic in unrecoverable_exception() because of the lost state. This occurred in Systemsim for Cell, but as far as I can see, it can theoretically occur on any machine that uses the system reset exception to get out of sleep state. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2006-10-25[POWERPC] cell: use ppc_md->power_save instead of cbe_idle_looparnd@arndb.de1-69/+27
This moves the cell idle function to use the default cpu_idle with a special power_save callback, like all other platforms except iSeries already do. It also makes it possible to disable this power_save function with a new powerpc-specific boot option "powersave=off". Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-25[POWERPC] cell: update Cell BE register definitionsDavid Erb1-3/+3
There are a few definitions that are required by subsequent patches, so add them here. The original patch is from David Erb, but is significantly cleaned up by Kevon Corry. Cc: Kevin Corry <kevcorry@us.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-30Remove obsolete #include <linux/config.h>Jörn Engel1-1/+0
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-06-21[POWERPC] cell: add RAS supportBenjamin Herrenschmidt1-83/+21
This is a first version of support for the Cell BE "Reliability, Availability and Serviceability" features. It doesn't yet handle some of the RAS interrupts (the ones described in iic_is/iic_irr), I'm still working on a proper way to expose these. They are essentially a cascaded controller by themselves (sic !) though I may just handle them locally to the iic driver. I need also to sync with David Erb on the way he hooked in the performance monitor interrupt. So that's all for 2.6.17 and I'll do more work on that with my rework of the powerpc interrupt layer that I'm hacking on at the moment. Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-29[PATCH] for_each_possible_cpu: powerpcKAMEZAWA Hiroyuki1-1/+1
for_each_cpu() actually iterates across all possible CPUs. We've had mistakes in the past where people were using for_each_cpu() where they should have been iterating across only online or present CPUs. This is inefficient and possibly buggy. We're renaming for_each_cpu() to for_each_possible_cpu() to avoid this in the future. This patch replaces for_each_cpu with for_each_possible_cpu. Signed-off-by: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-27[PATCH] powerpc: use guarded ioremap for cell on-chip mappingsArnd Bergmann1-1/+1
I'm not sure where the information came from, but I assumed that doing cache-inhibited mappings for mmio regions was sufficient. It seems we also need the guarded bit set, like everyone else, which is the default for ioremap. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-12[PATCH] powerpc: cell namespace cleanupArnd Bergmann1-1/+1
These symbols are only used in the file that they are defined in, so they should not be in the global namespace. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-09[PATCH] cell: enable pause(0) in cpu_idleArnd Bergmann1-0/+229
This patch enables support for pause(0) power management state for the Cell Broadband Processor, which is import for power efficient operation. The pervasive infrastructure will in the future enable us to introduce more functionality specific to the Cell's pervasive unit. From: Maximino Aguilar <maguilar@us.ibm.com> Signed-off-by: Arnd Bergmann <arndb@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>