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2021-11-29powerpc/85xx: Make c293_pcie_pic_init() staticMichael Ellerman1-1/+1
To fix the W=1 warning: linux/arch/powerpc/platforms/85xx/c293pcie.c:22:13: error: no previous prototype for ‘c293_pcie_pic_init’ Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20211124093254.1054750-3-mpe@ellerman.id.au
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner1-5/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-09-25powerpc: Convert fsl_rstcr_restart to a reset handlerAndrey Smirnov1-1/+0
Convert fsl_rstcr_restart into a function to be registered with register_reset_handler(). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> [scottwood: Converted mvme7100 as well] Signed-off-by: Scott Wood <oss@buserror.net>
2016-07-21powerpc: Move 32-bit probe() machine to later in the boot processBenjamin Herrenschmidt1-3/+1
This converts all the 32-bit platforms to use the expanded device-tree which is a pretty mechanical change. Unlike 64-bit, the 32-bit kernel didn't rely on platform initializations to setup the MMU since it sets it up entirely before probe_machine() so the move has comparatively less consequences though it's a bigger patch. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-08-17powerpc/85xx: Remove unused pci fixup hooks on c293pcieHou Zhiqiang1-4/+0
The c293pcie board is an endpoint device and it doesn't need PM, so remove hooks pcibios_fixup_phb and pcibios_fixup_bus. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-19fsl/pci: The new pci suspend/resume implementationWang Dongsheng1-0/+1
If we do nothing in suspend/resume, some platform PCIe ip-block can't guarantee the link back to L0 state from sleep, then, when we read the EP device will hang. Only we send pme turnoff message in pci controller suspend, and send pme exit message in resume, the link state will be normal. When we send pme turnoff message in pci controller suspend, the links will into l2/l3 ready, then, host cannot communicate with ep device, but pci-driver will call back EP device to save them state. So we need to change platform_driver->suspend/resume to syscore->suspend/resume. So the new suspend/resume implementation, send pme turnoff message in suspend, and send pme exit message in resume. And add a PME handler, to response PME & message interrupt. Change platform_driver->suspend/resume to syscore->suspend/resume. pci-driver will call back EP device, to save EP state in pci_pm_suspend_noirq, so we need to keep the link, until pci_pm_suspend_noirq finish. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-10-09powerpc: add explicit OF includesRob Herring1-0/+1
When removing prom.h include by of.h, several OF headers will no longer be implicitly included. Add explicit includes of of_*.h as needed. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Grant Likely <grant.likely@linaro.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Anatolij Gustschin <agust@denx.de> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Olof Johansson <olof@lixom.net> Cc: linuxppc-dev@lists.ozlabs.org
2013-08-23powerpc/85xx: Add C293PCIE board supportMingkai Hu1-0/+75
C293PCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. - 512KB platform SRAM in addition to 512K L2 Cache/SRAM - 512MB soldered DDR3 32bit memory - CPLD System Logic - 64MB x16 NOR flash and 4GB x8 NAND flash - 16MB SPI flash Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>