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2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner1-6/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2011-07-12powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and ↵Paul Mackerras1-4/+22
architecture bits This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to indicate that we have a usable hypervisor mode, and another to indicate that the processor conforms to PowerISA version 2.06. We also add another bit to indicate that the processor conforms to ISA version 2.01 and set that for PPC970 and derivatives. Some PPC970 chips (specifically those in Apple machines) have a hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode is not useful in the sense that there is no way to run any code in supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1 bits in HID4 are always 0, and we use that as a way of detecting that hypervisor mode is not useful. Where we have a feature section in assembly code around code that only applies on POWER7 in hypervisor mode, we use a construct like END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) The definition of END_FTR_SECTION_IFSET is such that the code will be enabled (not overwritten with nops) only if all bits in the provided mask are set. Note that the CPU feature check in __tlbie() only needs to check the ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called if we are running bare-metal, i.e. in hypervisor mode. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2008-09-15powerpc: Use LOAD_REG_IMMEDIATE only for constants on 64-bitPaul Mackerras1-2/+2
Using LOAD_REG_IMMEDIATE to get the address of kernel symbols generates 5 instructions where LOAD_REG_ADDR can do it in one, and will generate R_PPC64_ADDR16_* relocations in the output when we get to making the kernel as a position-independent executable, which we'd rather not have to handle. This changes various bits of assembly code to use LOAD_REG_ADDR when we need to get the address of a symbol, or to use suitable position-independent code for cases where we can't access the TOC for various reasons, or if we're not running at the address we were linked at. It also cleans up a few minor things; there's no reason to save and restore SRR0/1 around RTAS calls, __mmu_off can get the return address from LR more conveniently than the caller can supply it in R4 (and we already assume elsewhere that EA == RA if the MMU is on in early boot), and enable_64b_mode was using 5 instructions where 2 would do. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-16[POWERPC] powerpc: Enable DEEPNAP power savings mode on 970MPOlof Johansson1-0/+16
Without this patch, on an idle system I get: cpu-power-0:21.638 cpu-power-1:27.102 cpu-power-2:29.343 cpu-power-3:25.784 Total: 103.8W With this patch: cpu-power-0:11.730 cpu-power-1:17.185 cpu-power-2:18.547 cpu-power-3:17.528 Total: 65.0W If I lower HZ to 100, I can get it as low as: cpu-power-0:10.938 cpu-power-1:16.021 cpu-power-2:17.245 cpu-power-3:16.145 Total: 60.2W Another (older) Quad G5 went from 54W to 39W at HZ=250. Coming back out of Deep Nap takes 40-70 cycles longer than coming back from just Nap (which already takes quite a while). I don't think it'll be a performance issue (interrupt latency on an idle system), but in case someone does measurements feel free to report them. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-08-25Merge branch 'merge'Paul Mackerras1-0/+2
2006-08-25[POWERPC] Cleanup CPU initsOlof Johansson1-75/+24
Cleanup CPU inits a bit more, Geoff Levand already did some earlier. * Move CPU state save to cpu_setup, since cpu_setup is only ever done on cpu 0 on 64-bit and save is never done more than once. * Rename __restore_cpu_setup to __restore_cpu_ppc970 and add function pointers to the cputable to use instead. Powermac always has 970 so no need to check there. * Rename __970_cpu_preinit to __cpu_preinit_ppc970 and check PVR before calling it instead of in it, it's too early to use cputable. * Rename pSeries_secondary_smp_init to generic_secondary_smp_init since everyone but powermac and iSeries use it. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-08-25[POWERPC] Rename cpu_setup_power4.S to cpu_setup_ppc970.SOlof Johansson1-0/+225
Rename cpu_setup_power4.S to cpu_setup_ppc970.S, since that's really what it is. No functional or other changes. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>