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2013-01-29powerpc/fsl: Remove CONFIG_IRQ_ALL_CPUS from mpc85xx/mpc86xx defconfigScott Wood1-1/+0
While this should be harmless now that distribute_irqs obeys MPIC_SINGLE_DEST_CPU, there's no reason to enable this on mpc85xx/mpc86xx since MPIC_SINGLE_DEST_CPU will always be set. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-09-12powerpc/85xx: Add support for P5040DS boardTimur Tabi1-0/+1
Add support for the Freescale P5040DS Reference Board ("Superhydra"), which is similar to the P5020DS. Features of the P5040 are listed below, but not all of these features (e.g. DPAA networking) are currently supported. Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-08-23powerpc/fsl: fix "Failed to mount /dev: No such device" errorsKim Phillips1-0/+1
Yocto (Built by Poky 7.0) 1.2 root filesystems fail to boot, at least over nfs, with: Failed to mount /dev: No such device Configuring DEVTMPFS fixes it. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-08-23powerpc/fsl: update defconfigsKim Phillips1-20/+8
run make savedefconfig on fsl defconfigs. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-11powerpc/85xx: Update corenet32_smp_defconfigShengzhou Liu1-0/+8
- Enable NAND support - Enable CONFIG_PCI_MSI and CONFIG_MMC_SDHCI_OF Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10Revert "powerpc/p3060qds: Add support for P3060QDS board"Timur Tabi1-1/+0
This reverts commit 96cc017c5b7ec095ef047d3c1952b6b6bbf98943. The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10powerpc/fsl: Distribute interrupts on all CPUs by defaultKim Phillips1-0/+1
At least for crypto/IPSec, doing so provides users with a better performance experience out of the box. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-29powerpc/85xx: Enable I2C_CHARDEV and I2C_MPC options in defconfigsShaveta Leekha1-0/+1
Enable I2C char dev interface for user space testing of I2C controler. Enable the I2C driver on 64-bit builds (corenet64_smp_defconfig) as it was missing. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-04powerpc/85xx: re-enable ePAPR byte channel driver in corenet32_smp_defconfigTimur Tabi1-0/+1
Commit 7c4b2f09 (powerpc: Update mpc85xx/corenet 32-bit defconfigs) accidentally disabled the ePAPR byte channel driver in the defconfig for Freescale CoreNet platforms. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-04powerpc/fsl: Update defconfigs to enable some standard FSL HW featuresKumar Gala1-4/+5
corenet64_smp_defconfig: - enabled rapidio corenet32_smp_defconfig: - enabled hugetlbfs, rapidio mpc85xx_smp_defconfig: - enabled P1010RDB, hugetlbfs, SPI, SDHC, Crypto/CAAM mpc85xx_smp_defconfig: - enabled hugetlbfs, SPI, SDHC, Crypto/CAAM Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-12-07powerpc: Enable Hugetlb by default for 32-bit 85xx/corenetBecky Bruce1-0/+1
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-11-03powerpc/p3060qds: Add support for P3060QDS boardShengzhou Liu1-0/+1
The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC. The P3060 Processor combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. P3060QDS Board Overview: Memory subsystem: - 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus) - 128M Bytes NOR flash single-chip memory - 16M Bytes SPI flash - 8K Bytes AT24C64 I2C EEPROM Ethernet: - 4x1G + 4x1G/2.5G Ethernet controllers - 2xRGMII + 1xMII, three VSC8641 PHYs on board - Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3 PCIe: Two PCI Express 2.0 controllers/ports USB: Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board I2C: Four I2C controllers UART: Supports up to four UARTs RapidIO: Supports two serial RapidIO ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-11powerpc: Update mpc85xx/corenet 32-bit defconfigsBecky Bruce1-8/+0
Results from updates via make savedefconfig. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-06powerpc/85xx: Rename p2040_rdb.c to p2041_rdb.cMingkai Hu1-1/+1
There's only p2041rdb board for official release, but the p2041 silicon on the board can be converted to p2040 silicon without XAUI and L2 cache function, then the board becomes p2040rdb board. so we use the file name p2041_rdb.c to handle P2040RDB board and P2041RDB board which is also consistent with the board name under U-Boot. During the rename we make few other minor changes to the device tree: * Move USB phy setting into p2041si.dtsi as its SoC not board defined * Convert PCI clock-frequency to decimal to be more readable Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-08-30powerpc/85xx: enable caam crypto driver by defaultKim Phillips1-0/+1
corenet based SoCs have SEC4 h/w, so enable the SEC4 driver, caam, and the algorithms it supports, and disable the SEC2/3 driver, talitos. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-08powerpc/85xx: Add p2040 RDB board supportMingkai Hu1-0/+1
P2040RDB Specification: ----------------------- 2Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus) 128 Mbyte NOR flash single-chip memory 256 Kbit M24256 I2C EEPROM 16 Mbyte SPI memory SD connector to interface with the SD memory card dTSEC1: connected to the Vitesse SGMII PHY (VSC8221) dTSEC2: connected to the Vitesse SGMII PHY (VSC8221) dTSEC3: connected to the Vitesse SGMII PHY (VSC8221) dTSEC4: connected to the Vitesse RGMII PHY (VSC8641) dTSEC5: connected to the Vitesse RGMII PHY (VSC8641) I2C1: Real time clock, Temperature sensor I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors UART: supports two UARTs up to 115200 bps for console USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces PCIe: - Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1 - Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2 Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-08powerpc/85xx: add hypervisor config entries to corenet_smp_defconfigTimur Tabi1-0/+3
CONFIG_PPC_EPAPR_HV_BYTECHAN adds support for the Freescale hypervisor byte channel tty driver. CONFIG_VIRT_DRIVERS and CONFIG_FSL_HV_MANAGER add support for the Freescale hypervisor management driver. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-06-22powerpc: Add a defconfig for 'corenet' 32-bit platformsKumar Gala1-0/+183
The e500mc and e5500 based cores are only available on corenet based SoCs. We use this name for the P204x, P3040, P4040, P4080, P50x0 SoCs and any future processors in these families. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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