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2020-09-29net: mscc: ocelot: add definitions for VCAP IS1 keys, actions and targetVladimir Oltean1-1/+2
As a preparation step for the offloading to IS1, let's create the infrastructure for talking with this hardware block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-28PCI: MSI: Fix Kconfig dependencies for PCI_MSI_ARCH_FALLBACKSThomas Gleixner1-1/+1
The unconditional selection of PCI_MSI_ARCH_FALLBACKS has an unmet dependency because PCI_MSI_ARCH_FALLBACKS is defined in a 'if PCI' clause. As it is only relevant when PCI_MSI is enabled, update the affected architecture Kconfigs to make the selection of PCI_MSI_ARCH_FALLBACKS depend on 'if PCI_MSI'. Fixes: 077ee78e3928 ("PCI/MSI: Make arch_.*_msi_irq[s] fallbacks selectable") Reported-by: Qian Cai <cai@redhat.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Vasily Gorbik <gor@linux.ibm.com> Links: https://lore.kernel.org/r/cdfd63305caa57785b0925dd24c0711ea02c8527.camel@redhat.com
2020-09-28KVM: MIPS: clean up redundant kvm_run parameters in assemblyTianjia Zhang5-18/+14
In the current kvm version, 'kvm_run' has been included in the 'kvm_vcpu' structure. For historical reasons, many kvm-related function parameters retain the 'kvm_run' and 'kvm_vcpu' parameters at the same time. This patch does a unified cleanup of these remaining redundant parameters. Signed-off-by: Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Reviewed-by: Huacai Chen <chenhc@lemote.com> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20200623131418.31473-6-tianjia.zhang@linux.alibaba.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-27MIPS: idle: Add prototype for function check_waitPujin Shi1-0/+2
This commit adds a prototype to fix warning at W=1: arch/mips/kernel/idle.c:126:13: error: no previous prototype for 'check_wait' [-Werror=missing-prototypes] Signed-off-by: Pujin Shi <shipujin.t@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-27MIPS: Increase range of CONFIG_FORCE_MAX_ZONEORDERPaul Cercueil1-1/+1
There is nothing that prevents us from using lower maximum values. It's something that we actually want, when using bigger page sizes on devices with low RAM. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-27MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.周琰杰 (Zhou Yanjie)1-0/+2
1.Fix bugs when detecting ways value of JZ4775's L2 cache. 2.Fix bugs when detecting sets value and ways value of X1000E's L2 cache. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-27MIPS: Ingenic: Add system type for new Ingenic SoCs.周琰杰 (Zhou Yanjie)2-0/+14
Add JZ4775, X1000E, X2000, and X2000E system type for cat /proc/cpuinfo to give out JZ4775, X1000E, X2000 and X2000E. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-25Merge tag 'mips_fixes_5.9_3' of ↵Linus Torvalds4-17/+14
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS fixes from Thomas Bogendoerfer: - fixed FP register access on Loongsoon-3 - added missing 1074 cpu handling - fixed Loongson2ef build error * tag 'mips_fixes_5.9_3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: BCM47XX: Remove the needless check with the 1074K MIPS: Add the missing 'CPU_1074K' into __get_cpu_type() MIPS: Loongson2ef: Disable Loongson MMI instructions MIPS: Loongson-3: Fix fp register access if MSA enabled
2020-09-25dma-mapping: add a new dma_alloc_pages APIChristoph Hellwig1-5/+2
This API is the equivalent of alloc_pages, except that the returned memory is guaranteed to be DMA addressable by the passed in device. The implementation will also be used to provide a more sensible replacement for DMA_ATTR_NON_CONSISTENT flag. Additionally dma_alloc_noncoherent is switched over to use dma_alloc_pages as its backend. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> (MIPS part)
2020-09-25dma-mapping: remove dma_cache_syncChristoph Hellwig3-8/+0
All users are gone now, remove the API. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> (MIPS part)
2020-09-25Merge branch 'master' of ↵Christoph Hellwig11-12/+35
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into dma-mapping-for-next Pull in the latest 5.9 tree for the commit to revert the V4L2_FLAG_MEMORY_NON_CONSISTENT uapi addition.
2020-09-23MIPS: BCM47XX: Remove the needless check with the 1074KWei Li1-1/+1
As there is no known soc powered by mips 1074K in bcm47xx series, the check with 1074K is needless. So just remove it. Link: https://wireless.wiki.kernel.org/en/users/Drivers/b43/soc Fixes: 442e14a2c55e ("MIPS: Add 1074K CPU support explicitly.") Signed-off-by: Wei Li <liwei391@huawei.com> Acked-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-23MIPS: Add the missing 'CPU_1074K' into __get_cpu_type()Wei Li1-0/+1
Commit 442e14a2c55e ("MIPS: Add 1074K CPU support explicitly.") split 1074K from the 74K as an unique CPU type, while it missed to add the 'CPU_1074K' in __get_cpu_type(). So let's add it back. Fixes: 442e14a2c55e ("MIPS: Add 1074K CPU support explicitly.") Signed-off-by: Wei Li <liwei391@huawei.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-23MIPS: Loongson2ef: Disable Loongson MMI instructionsJiaxun Yang1-0/+4
It was missed when I was forking Loongson2ef from Loongson64 but should be applied to Loongson2ef as march=loongson2f will also enable Loongson MMI in GCC-9+. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Fixes: 71e2f4dd5a65 ("MIPS: Fork loongson2ef from loongson64") Reported-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: stable@vger.kernel.org # v5.8+ Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-23Revert "MIPS: OCTEON: use devm_platform_ioremap_resource"Thomas Bogendoerfer1-1/+9
This reverts commit 0ee69c589ec8659560910815f32c13af8587a779. Resource is still needed later in the code, so using devm_platform_ioremap_resource is no win at all. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-22fs: remove compat_sys_mountChristoph Hellwig2-2/+2
compat_sys_mount is identical to the regular sys_mount now, so remove it and use the native version everywhere. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-09-22MIPS: Loongson-3: Fix fp register access if MSA enabledHuacai Chen1-16/+8
If MSA is enabled, FPU_REG_WIDTH is 128 rather than 64, then get_fpr64() /set_fpr64() in the original unaligned instruction emulation code access the wrong fp registers. This is because the current code doesn't specify the correct index field, so fix it. Fixes: f83e4f9896eff614d0f2547a ("MIPS: Loongson-3: Add some unaligned instructions emulation") Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Pei Huang <huangpei@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-22Merge branch 'x86-seves-for-paolo' of ↵Paolo Bonzini11-42/+62
https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into HEAD
2020-09-21MIPS: kexec: Add crashkernel=YM handlingYouling Tang1-3/+21
When the kernel crashkernel parameter is specified with just a size, we are supposed to allocate a region from RAM to store the crashkernel. However, MIPS merely reserves physical address zero with no checking that there is even RAM there. Fix this by lifting similar code from x86, importing it to MIPS with the MIPS specific parameters added. In the absence of any platform specific information, we allocate the crashkernel region from the first 512MB of physical memory (limited to CKSEG0 or KSEG0 address range). When X is not specified, crash_base defaults to 0 (crashkernel=YM@XM). E.g. without this patch: The environment as follows: [ 0.000000] MIPS: machine is loongson,loongson64c-4core-ls7a ... [ 0.000000] Kernel command line: root=/dev/sda2 crashkernel=96M ... The warning as follows: [ 0.000000] Invalid memory region reserved for crash kernel And the iomem as follows: 00200000-0effffff : System RAM 00200000-00b47f87 : Kernel code 00b47f88-00dfffff : Kernel data 00e60000-01f73c7f : Kernel bss 1a000000-1bffffff : pci@1a000000 ... With this patch: After increasing crash_base <= 0 handling. And the iomem as follows: 00200000-0effffff : System RAM 00200000-00b47f87 : Kernel code 00b47f88-00dfffff : Kernel data 00e60000-01f73c7f : Kernel bss 04000000-09ffffff : Crash kernel 1a000000-1bffffff : pci@1a000000 ... Signed-off-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: Loongson64: Add UART node for LS7A PCHTiezhu Yang1-0/+39
When I update the latest kernel on the Loongson platform used with LS7A bridge chip, the serial console has no output, this is because the machine uses LS7A UART0 instead of CPU UART0, add UART node for LS7A PCH to enhance the compatibility. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: Ingenic: Add CPU nodes for Ingenic SoCs.周琰杰 (Zhou Yanjie)6-1/+93
Add 'cpus' node to the jz4725b.dtsi, jz4740.dtsi, jz4770.dtsi, jz4780.dtsi, x1000.dtsi, and x1830.dtsi files. Tested-by: H. Nikolaus Schaller <hns@goldelico.com> Tested-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: malta: remove mach-malta/malta-dtshim.h header fileThomas Bogendoerfer3-26/+2
To clean up mach-* directories move external declaration of malta_dt_shim() to mips-boards/malta.h and remove malta-dtshim.h. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: malta: remove unused header fileThomas Bogendoerfer1-33/+0
Remove unused heasder file asm/mach-malta/malta-pm.h. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: alchemy: remove unused ALCHEMY_GPIOINT_AU1000Thomas Bogendoerfer1-7/+0
Remove unused config option ALCHEMY_GPIOINT_AU1000. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: alchemy: remove unused ALCHEMY_GPIOINT_AU1300Thomas Bogendoerfer2-141/+0
Remove unused config option ALCHEMY_GPIOINT_AU1300 and related code. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: SGI-IP30: Move irq bits to better header filesThomas Bogendoerfer4-87/+67
Move HEART specific parts of mach-ip30/irq.h to asm/sgi/heart.h and IP30 specific parts to sgi-ip30/ip30-common.h. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: Loongson-3: Calculate ra properly when unwinding the stackHuacai Chen1-1/+15
Loongson-3 has 16-bytes load/store instructions: gslq and gssq. This patch calculate ra properly when unwinding the stack, if ra is saved by gssq and restored by gslq. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: Loongson-3: Enable COP2 usage in kernelHuacai Chen6-7/+19
Loongson-3's COP2 is Multi-Media coprocessor, it is disabled in kernel mode by default. However, gslq/gssq (16-bytes load/store instructions) overrides the instruction format of lwc2/swc2. If we wan't to use gslq/ gssq for optimization in kernel, we should enable COP2 usage in kernel. Please pay attention that in this patch we only enable COP2 in kernel, which means it will lose ST0_CU2 when a process go to user space (try to use COP2 in user space will trigger an exception and then grab COP2, which is similar to FPU). And as a result, we need to modify the context switching code because the new scheduled process doesn't contain ST0_CU2 in its THERAD_STATUS probably. For zboot, we disable gslq/gssq be generated by toolchain. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: context switch: Use save/restore instead of set/clear for Status.CU2Huacai Chen1-1/+3
Some processors (such as Loongson-3) need to enable CU2 in kernel mode, current set/clear method will lose Status.CU2 during context switching, so use save/restore method instead. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: kernel: include probes-common.h header in branch.cPujin Shi1-0/+2
arch/mips/kernel/branch.c:876:5: error: no previous prototype for '__insn_is_compact_branch' [-Werror=missing-prototypes] Signed-off-by: Pujin Shi <shipujin.t@gmail.com> Signed-off-by: Pujin Shi <shipj@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: Make setup_elfcorehdr and setup_elfcorehdr_size staticJason Yan1-1/+1
This addresses the following sparse warning: arch/mips/kernel/setup.c:446:33: warning: symbol 'setup_elfcorehdr_size' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: configs: Regenerate configs of Ingenic boardsPaul Cercueil6-35/+11
For each board the MACH_INGENIC_SOC option was selected instead of MACH_INGENIC. Nothing else was changed in the menuconfig. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: jz4740: Rename jz4740 folders to ingenicPaul Cercueil4-2/+2
Now that all the jz4740 platform code has been removed, and we're left with only a Kconfig and the cpu-feature-overrides.h file, finalize the cleanup process by renaming the jz4740 and include/mach-jz4740 folders to ingenic and include/mach-ingenic. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: jz4740: Drop all obsolete filesPaul Cercueil4-170/+0
Support for Ingenic SoCs is now provided by the arch/mips/generic/ code, so all files in the arch/mips/jz4740/ folder can dropped, except for the Kconfig, and the cpu-feature-overrides.h header file. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: generic: Add support for Ingenic SoCsPaul Cercueil7-18/+149
Add support for Ingenic SoCs in arch/mips/generic/. The Kconfig changes are here to ensure that it is possible to compile either a generic kernel that supports Ingenic SoCs, or a Ingenic-only kernel, both using the same code base, to avoid duplicated code. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: generic: Increase NR_IRQS to 256Paul Cercueil1-1/+1
128 IRQs is not enough to support Ingenic SoCs. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: generic: Add support for zbootPaul Cercueil2-0/+2
There is no reason we can't create compressed kernels here, so select the option SYS_SUPPORTS_ZBOOT. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: generic: Support booting with built-in or appended DTBPaul Cercueil1-5/+4
The plat_get_fdt() checked that the kernel was booted using UHI before reading the 'fw_passed_dtb' variable. However, this variable is also set when the DT has been appended, or when it has been built into the kernel. Support these usecases by removing the UHI check. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: generic: Init command line with fw_init_cmdline()Paul Cercueil1-1/+1
The function bootcmdline_init() in arch/mips/kernel/setup.c will populate the boot_command_line string using the parameters hardcoded in the kernel, and those provided in the devicetree file. Then, it would append the content of the arcs_cmdline variable, which is filled by the board's plat_mem_setup() function. The plat_mem_setup() function for the generic MIPS board would just copy the current boot_command_line to arcs_cmdline, which is nonsense for two reasons: - the result will be appended to the boot_command_line anyway, so all it does is duplicate every single parameter on the command line; - the code did not perform at all what it's supposed to, which is to retrieve the parameters passed by the bootloader. Fix this by calling fw_init_cmdline() in plat_mem_setup(), which will properly initialize arcs_cmdline to the parameters passed by the bootloader. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: generic: Allow boards to set system typePaul Cercueil1-0/+5
Check for the system_type variable in the get_system_type() function. If non-NULL, return it as the system type. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: Kconfig: add MIPS_GENERIC_KERNEL symbolPaul Cercueil2-3/+7
The MIPS_GENERIC symbol now won't select any other configuration option. The MIPS_GENERIC_KERNEL will select all the options that the previous MIPS_GENERIC option did select, and will select MIPS_GENERIC as well. The whole point of this, is that it now becomes possible to compile a kernel for a SoC supported by the arch/mips/generic/ code, without making that kernel generic itself. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: cpu-probe: ingenic: Fix broken BUG_ONPaul Cercueil1-1/+1
The previous code was doing: BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); This only worked as the "cpu_has_counter" macro was overridden in <cpu-feature-overrides.h>. The default "cpu_has_counter" macro is non-constant, which triggered the BUG_ON() independently of the value returned by the macro. What we want to check here, is that *if* the macro was overridden to a compile-time constant, then must be defined to zero, otherwise it's a bug. So the correct check is: BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter); Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: cpu-probe: Mark XBurst CPU as having vtagged cachesPaul Cercueil1-0/+3
XBurst CPUs present in Ingenic SoCs have virtually tagged caches, according to the <cpu-features-override.h> header. Add that information to cpu_probe_ingenic(). Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WAPaul Cercueil2-6/+2
Previously, in cpu_probe_ingenic(), c->writecombine was set to _CACHE_UNCACHED_ACCELERATED, but this macro was defined differently when CONFIG_MACH_INGENIC was set. This made it impossible to support multiple CPUs. Address this issue by setting c->writecombine to _CACHE_CACHABLE_WA directly and removing the dependency on CONFIG_MACH_INGENIC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: configs: lb60: Fix defconfig not selecting correct boardPaul Cercueil1-0/+1
Since INGENIC_GENERIC_BOARD was introduced, the JZ4740_QI_LB60 option is no longer the default, so the symbol has to be selected by the defconfig, otherwise the kernel built will be for a generic Ingenic board and won't have the Device Tree blob built-in. Cc: stable@vger.kernel.org # v5.7 Fixes: 62249209a772 ("MIPS: ingenic: Default to a generic board") Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: Loongson64: Increase NR_IRQS to 320Huacai Chen1-1/+2
Modernized Loongson64 uses a hierarchical organization for interrupt controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) is not enough to represent all interrupts, so let's increase NR_IRQS to 320 (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256). Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: netlogic: Remove unused codeYouling Tang1-15/+0
Remove some unused code. Signed-off-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: OCTEON: use devm_platform_ioremap_resourceQinglang Miao1-9/+1
Note that error handling on the result of a call to platform_get_resource() is unneeded when the value is passed to devm_ioremap_resource(), so remove it. Then use the helper function that wraps the calls to platform_get_resource() and devm_ioremap_resource() together. Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: pci: use devm_platform_ioremap_resource_bynameZhang Qilong3-11/+7
Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately. Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: Correct the header guard of r4k-timer.hWei Li1-3/+3
Rename the header guard of r4k-timer.h from __ASM_R4K_TYPES_H to __ASM_R4K_TIMER_H what corresponding with the file name. Signed-off-by: Wei Li <liwei391@huawei.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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