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2012-11-11MIPS: lantiq: adds code for booting GPHYJohn Crispin2-0/+39
The XRX200 family of SoCs has embedded gigabit PHYs. This patch adds code to boot them up. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4522
2012-11-11MIPS: lantiq: adds xrx200 ethernet clock definitionJohn Crispin1-0/+4
Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4521
2012-11-11MIPS: lantiq: verbose init of dma coreJohn Crispin1-1/+8
Print the hardware revision and port/channel info when starting the dma core. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4520
2012-11-11MIPS: lantiq: fix bootselect bits on XRX200 SoCJohn Crispin1-7/+15
The XRX200 SoC family has a different register layout for reading the boot selection bits. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4519
2012-11-11MIPS: lantiq: unbreak devicetree initJohn Crispin1-4/+1
The bootmem was incorrectly freed resulting in lots of dangling pointers. Additionally we should use of_platform_populate() as the Documentaion tells us to do so. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4518
2012-11-09MIPS: Loongson1B: Fix a typoKelvin Cheung1-1/+1
Fix a typo in the code. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4434 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Loongson1B: Update stmmac_mdio_bus_dataKelvin Cheung1-1/+0
Update stmmac_mdio_bus_data accordingly due to the upstream change. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4433 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Loongson1B: improve ls1x_serial_setup()Kelvin Cheung3-9/+7
Improve ls1x_serial_setup(). Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4432 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Loongson1B: use common clock infrastructure instead of private APIsKelvin Cheung4-159/+8
Use common clock infrastructure instead of private APIs. 1. Enable COMMON_CLK in the Kconfig. 2. Remove private clock APIs, which are replaced by the code in drivers/clk/clk-ls1x.c. 3. Modify header file for drivers/clk/clk-ls1x.c. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4431 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Netlogic: Support for XLR/XLS Fast Message NetworkGanesan Ramalingam12-12/+1020
On XLR/XLS, the cpu cores communicate with fast on-chip devices (e.g. network accelerator, security engine etc.) using the Fast Messaging Network(FMN). The FMN queues and credits needs to be configured and intialized before it can be used. The co-processor 2 on XLR/XLS CPU cores has registers for FMN access, and the XLR/XLS has custom instructions for sending and loading messages. The FMN can deliver also per-cpu interrupts when messages are available at the CPU. This patch adds FMN initialization, adds interrupt setup and handling, and also provides support for sending and receiving FMN messages. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4468 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Netlogic: PIC IRQ handling update for multi-chipJayachandran C5-115/+103
Create struct nlm_pic_irq for interrupts handled by the PIC. This simplifies IRQ handling for multi-SoC as well as the single SoC cases. Also split the setup of percpu and PIC interrupts so that we can configure the PIC interrupts for every node. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4467 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Netlogic: Make number of nodes configurableJayachandran C4-5/+90
There can be 1, 2 or 4 SoCs(nodes) in a multi-chip XLP board. Add an option for multi-chip boards in case of XLP, and make the number of nodes configurable. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4470 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Netlogic: Support for multi-chip configurationJayachandran C12-86/+176
Upto 4 Netlogic XLP SoCs can be connected over ICI links to form a coherent multi-node system. Each SoC has its own set of on-chip devices including PIC. To support this, add a per SoC stucture and use it for the PIC and SYS block addresses instead of using global variables. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4469 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Netlogic: Move from u32 cpumask to cpumask_tJayachandran C6-55/+86
Initial code to support more than 32 cpus. The platform CPU mask is updated from 32-bit mask to cpumask_t. Convert places that use cpu_/cpus_ functions to use cpumask_* functions. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4464 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Netlogic: Update PIC access functionsJayachandran C1-33/+7
Remove unused and trivial PIC accesss functions, update nlm_pic_send_ipi() and nlm_set_irt_to_cpu() to use similar logic, and use correct type for reg in nlm_pic_disable_irt(). Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4463 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Netlogic: Pass cpuid to early_init_secondaryJayachandran C2-2/+4
The cpuid was not passed into early_init_secondary even though the comment indicated that it will be. Fix this. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4458 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Netlogic: Fix interrupt table entry initJayachandran C1-1/+1
Used the hardware thread id passed in while writing to IRT in nlm_pic_init_irt() Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4465 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Netlogic: Fix DMA zone selection for 64-bitJayachandran C1-2/+2
Fix Kconfig for both XLR and XLP to select ZONE_DMA32 (instead of ZONE_DMA) in case of 64-bit compilation. This can be used for devices that can only do DMA to 32-bit address. ZONE_DMA is not useful on XLR or XLP. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4466 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Netlogic: Move fdt init to plat_mem_setupJayachandran C1-13/+14
At this point early printk is available, so debugging device tree issues is easier. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4460 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Netlogic: Enable SUE bit in coresJayachandran C1-1/+1
Enable Speculative Unmap Enable bit, which will enable speculative L2 cache requests for unmapped memory. This should give better performance for kernel code/data which is in KSEG0 Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4461 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Netlogic: select MIPSR2 for XLPJayachandran C1-1/+2
This allows us to use the r2 optimized code from kernel headers while compilation. Disable PGD_C0_CONTEXT option for XLP, which does not work. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4456 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: perf: Add XLP support for hardware perf.Zi Shen Lim2-1/+125
Add support for XLP performance counters register in perf. Update mips/Kconfig so that perf events can be selected for XLP. Signed-off-by: Zi Shen Lim <zlim@netlogicmicro.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4457 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: oprofile: Support for XLR/XLS processorsMadhusudan Bhat3-0/+31
Add support for XLR and XLS processors in MIPS Oprofile code. These processors are multi-threaded and have two counters per core. Each counter can track either all the events in the core (global mode), or events in just one thread. We use the counters in the global mode, and use only the first thread in each core to handle the configuration etc. Signed-off-by: Madhusudan Bhat <mbhat@netlogicmicro.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4471 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: BCM63XX: move nvram functions into their own fileJonas Gorski5-80/+154
Refactor nvram related functions into its own unit for easier expansion and exposure of the values to other drivers. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4516 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: BCM63XX: use the new reset helperJonas Gorski2-27/+11
Use the new reset helper where appropriate. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4453 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: BCM63XX: add core reset helperJonas Gorski3-3/+247
Add a reset helper for resetting the different cores. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4455 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: BCM63XX: add softreset register description for BCM6358Jonas Gorski1-0/+10
The softreset register description for BCM6358 was missing, so add it. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4454 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: BCM63XX: add and use a clock for PCIeJonas Gorski2-5/+25
Add a PCIe clock and use that instead of directly touching the clock control register. While at it, fail if there is no such clock. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Acked-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4452 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: BCM47xx: sprom: read values without prefix as fallbackHauke Mehrtens3-332/+449
There are bcma based devices like the Linksys E2000 out there, which do have one ieee80211 core, but no PCIe core and they are using no prefixes for the sprom. In addition some values like boardtype are stored without a prefix for the main SoC chip also when they have an additional PCIe wifi chip with an own boardtype var on some devices. The Ethernet addresses are now also read out correctly without a prefix so calling bcm47xx_fill_sprom_ethernet is not needed any more. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4364 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: BCM47XX: read sprom without prefix if no ieee80211 coreHauke Mehrtens1-0/+2
If there is no ieee80211 core on the devices like on the BCM4706 read out the sprom and the other data without using a prefix. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4361 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: BCM47xx: read out full board dataHauke Mehrtens1-20/+14
Read out the full board data independently of the sprom version. Now we also get the full boardflags and so on if sromrev is not set and our code would assume a rev 1 device. When a nvram option is not set because it is not there this is no problem. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4363 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: BCM47XX: improve memory size detectionHauke Mehrtens1-4/+6
The memory size is detected by finding a place where it repeats in memory. Currently we are just checking when the function prom_init is seen again, but it is better to check for a bigger part of the memory to decrease the chance of wrong results. This should fix a problem we saw in OpenWrt, where the detected available memory decreed on some devices when doing a soft reboot. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4362 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: BCM47XX: ignore last memory pageHauke Mehrtens1-0/+10
Ignoring the last page when ddr size is 128M. Cached accesses to last page is causing the processor to prefetch using address above 128M stepping out of the ddr address space. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4365 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Move processing of coherency kernel parameters earlierShane McDonald1-4/+4
Commit 97ce2c88f9ad42e3c60a9beb9fca87abf3639faa (jump-label: initialize jump-label subsystem much earlier) caused MIPS to break, so this was resolved with commit 6650df3c380e0db558dbfec63ed860402c6afb2a (MIPS: Move cache setup to setup_arch().). Unfortunately, after this commit, the coherency kernel parameters, cca and coherentio, are no longer processed before their values are used. This patch fixes this problem by marking them as early_param, which results in them being processed before they are needed. Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com> Acked-by: David Daney <david.daney@cavium.com> Cc: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/3961 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09mips/octeon: 16-Bit NOR flash was not being detected during bootCharles Hardin1-1/+2
The cavium code assumed that all NOR on the boot bus was an 8-bit NOR part and hardcoded the bankwidth. The simple solution was to add the code that queries the configuration register for the width of the bus that has been hardware strapped to the Cavium. This allows both 8-bit and 16-bit parts to be discovered during boot. Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: Charles Hardin <ckhardin@exablox.com> Patchwork: http://patchwork.linux-mips.org/patch/4323 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: tlbex: Fix section mismatchesKevin Cernekee1-2/+6
The new functions introduced in commit 02a5417751 (MIPS: tlbex: Deal with re-definition of label) should be marked __cpuinit, to eliminate a warning that can pop up when CONFIG_EXPORT_UASM is disabled: LD arch/mips/mm/built-in.o WARNING: arch/mips/mm/built-in.o(.text+0x2a4c): Section mismatch in reference from the function uasm_bgezl_hazard() to the function .cpuinit.text:uasm_il_bgezl() The function uasm_bgezl_hazard() references the function __cpuinit uasm_il_bgezl(). This is often because uasm_bgezl_hazard lacks a __cpuinit annotation or the annotation of uasm_il_bgezl is wrong. WARNING: arch/mips/mm/built-in.o(.text+0x2a68): Section mismatch in reference from the function uasm_bgezl_label() to the function .cpuinit.text:uasm_build_label() The function uasm_bgezl_label() references the function __cpuinit uasm_build_label(). This is often because uasm_bgezl_label lacks a __cpuinit annotation or the annotation of uasm_build_label is wrong. (This warning might not occur if the function was inlined.) Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4517 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Make irqflags.h functions preempt-safe for non-mipsr2 cpusJim Quinlan3-133/+253
For non MIPSr2 processors, such as the BMIPS 5000, calls to arch_local_irq_disable() and others may be preempted, and in doing so a stale value may be restored to c0_status. This fix disables preemption for such processors prior to the call and enables it after the call. Those functions that needed this fix have been "outlined" to mips-atomic.c, as they are no longer good candidates for inlining. This bug was observed in a BMIPS 5000, occuring once every few hours in a continuous reboot test. It was traced to the write_lock_irq() function which was being invoked in release_task() in exit.c. By placing a number of "nops" inbetween the mfc0/mtc0 pair in arch_local_irq_disable(), which is called by write_lock_irq(), we were able to greatly increase the occurance of this bug. Similarly, the application of this commit silenced the bug. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Cc: Kevin Cernekee cernekee@gmail.com Cc: Jim Quinlan <jim2101024@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4321/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-11-09MIPS: Remove irqflags.h dependency from bitops.hJim Quinlan5-83/+214
The "else clause" of most functions in bitops.h invoked raw_local_irq_{save,restore}() and in doing so had a dependency on irqflags.h. This fix moves said code to bitops.c, removing the dependency. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Cc: Kevin Cernekee cernekee@gmail.com Cc: Jim Quinlan <jim2101024@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4320/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-11-09MIPS: bitops.h: Change use of 'unsigned short' to 'int'Jim Quinlan1-7/+7
[ralf@linux-mips.org: No functional change but it's consistent with how use types elsewhere in the code.] Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Cc: Kevin Cernekee cernekee@gmail.com Cc: Jim Quinlan <jim2101024@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4319/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-11-09MIPS: compat: Delete now unused TIF_32BIT.Ralf Baechle1-6/+0
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-11-09MIPS: compat: Implement is_compat_task() by testing for 32-bit address space.Ralf Baechle1-1/+1
So far is_compat_task() was testing for 32-bit registers if O32 support was enabled and if O32 support was disabled but N32 enabled it was testing for 32-bit address space. So if both O32 and N32 were enabled a N32 task was not considered a compat task, whops. This still leaves potential cases where O32 and N32 need different treatment unsolved. But that's another commit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-11-09MIPS: compat: Fix use of TIF_32BIT_ADDR vs _TIF_32BIT_ADDRRalf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-10-18Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds8-25/+68
Pull MIPS fixes from Ralf Baechle: "Random small fixes across the MIPS code." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: CMP: Fix physical core number calculation logic MIPS: JZ4740: Forward declare struct uart_port in header. MIPS: JZ4740: Fix '#include guard' in serial.h MIPS: hugetlbfs: Fix hazard between tlb write and pagemask restoration. MIPS: Restore pagemask after dumping the TLB. MIPS: Hugetlbfs: Handle huge pages correctly in pmd_bad() MIPS: R5000: Fix TLB hazard handling. MIPS: tlbex: Deal with re-definition of label MIPS: Make __{,n,u}delay declarations match definitions and generic delay.h
2012-10-18MIPS: CMP: Fix physical core number calculation logicjerin jacob1-1/+1
The CPUNum Field in EBase register is 10bit wide, so after 1 bit right shift, the mask value should be 0x1ff. Signed-off-by: jerin jacob <jerinjacobk@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4420/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-10-17MIPS: JZ4740: Forward declare struct uart_port in header.Ralf Baechle1-0/+2
As suggested by Geert Uytterhoeven <geert@linux-m68k.org>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: linux-mips@linux-mips.org Cc: Lars-Peter Clausen <lars@metafoo.de>
2012-10-17MIPS: JZ4740: Fix '#include guard' in serial.hAntony Pavlov1-0/+1
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Cc: linux-mips@linux-mips.org Cc: Lars-Peter Clausen <lars@metafoo.de> Patchwork: https://patchwork.linux-mips.org/patch/4424/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-10-17UAPI: Place comments in empty arch Kbuilds to make them non-emptyDavid Howells1-0/+1
Place comments in: arch/mips/include/asm/Kbuild arch/tile/include/arch/Kbuild to make them non-empty so that the patch program doesn't remove them when it reduces them to nothing. Possibly they should be just deleted, but it's possible that they'll acquire generic-y or genhdr-y lines in future, so I'm keeping them around for the moment. Note that MIPS will compile happily if the file is deleted instead. I haven't tested TILE, but I suspect it will be the same there. Signed-off-by: David Howells <dhowells@redhat.com> cc: Ralf Baechle <ralf@linux-mips.org> cc: Chris Metcalf <cmetcalf@tilera.com>
2012-10-17MIPS: hugetlbfs: Fix hazard between tlb write and pagemask restoration.Ralf Baechle1-0/+1
On some CPU the write to pagemask might complete before the TLB write instruction reads from the pagemask register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-10-17MIPS: Restore pagemask after dumping the TLB.Ralf Baechle1-1/+3
Or bad things might happen if the last TLB entry isn't a basic size page. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-10-17MIPS: Hugetlbfs: Handle huge pages correctly in pmd_bad()Ralf Baechle1-1/+14
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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