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2010-12-16MIPS: FDT size is a be32Thomas Chou1-1/+1
The totalsize field was be32. And the reserve bootmem would cause failure. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> To: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: grant.likely@secretlab.ca Cc: David Daney <ddaney@caviumnetworks.com> Cc: Dezhong Diao <dediao@cisco.com> Patchwork: https://patchwork.linux-mips.org/patch/1838/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: Fix CP0 COUNTER clockevent raceKevin Cernekee1-1/+1
Consider the following test case: write_c0_compare(read_c0_count()); Even if the counter doesn't increment during execution, this might not generate an interrupt until the counter wraps around. The CPU may perform the comparison each time CP0 COUNT increments, not when CP0 COMPARE is written. If mips_next_event() is called with a very small delta, and CP0 COUNT increments during the calculation of "cnt += delta", it is possible that CP0 COMPARE will be written with the current value of CP0 COUNT. If this is detected, the function should return -ETIME, to indicate that the interrupt might not have actually gotten scheduled. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1836/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: Fix regression on BCM4710 processor detectionKevin Cernekee2-7/+4
BCM4710 uses the BMIPS32 core (like BCM6345), not the MIPS 4Kc core as was previously believed. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Tested-by: Alexandros C. Couloumbis <alex@ozo.com> Patchwork: https://patchwork.linux-mips.org/patch/1837/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: JZ4740: Fix pcm device nameLars-Peter Clausen1-1/+1
As part the ASoC multi-component patch (commit f0fba2ad) the jz4740 pcm driver was renamed to 'jz4740-pcm-audio'. Adjust the device name accordingly. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1770/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: Separate two consecutive loads in memset.STony Wu1-2/+2
partial_fixup is used in noreorder block. Separating two consecutive loads can save one cycle on processors with GPR intrelock and can fix load-use on processors that need a load delay slot. Also do so for fwd_fixup. [Ralf: Only R2000/R3000 class processors are lacking the the load-user interlock and even some of those got it retrofitted. With R2000/R3000 being fairly uncommon these days the impact of this bug should be minor.] Signed-off-by: Tony Wu <tung7970@gmail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1768/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: Send proper signal and siginfo on FP emulator faults.David Daney2-30/+130
We were unconditionally sending SIGBUS with an empty siginfo on FP emulator faults. This differs from what happens when real floating point hardware would get a fault. For most faults we need to send SIGSEGV with the faulting address filled in in the struct siginfo. Reported-by: Camm Maguire <camm@maguirefamily.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: Camm Maguire <camm@maguirefamily.org> Patchwork: https://patchwork.linux-mips.org/patch/1727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: AR7: Fix loops per jiffies on TNETD7200 devicesFlorian Fainelli3-6/+7
TNETD7200 run their CPU clock faster than the default CPU clock we assume. In order to have the correct loops per jiffies settings, initialize clocks right before setting mips_hpt_frequency. As a side effect, we can no longer use msleep in clocks.c which requires other parts of the kernel to be initialized, so replace these with mdelay. Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1749/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: AR7: Fix double ar7_gpio_init declarationFlorian Fainelli1-2/+0
Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1748/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: Rework GENERIC_HARDIRQS Kconfig.David Daney1-14/+2
Recent changes to CONFIG_GENERIC_HARDIRQS have caused us to start getting: warning: (SMP && SYS_SUPPORTS_SMP) selects IRQ_PER_CPU which has unmet direct dependencies (HAVE_GENERIC_HARDIRQS) Rearranging our Kconfig quiets the message. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: Thomas Gleixner <tglx@linutronix.de> Patchwork: https://patchwork.linux-mips.org/patch/1757/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: Alchemy: Add return value check for strict_strtoul()Yoichi Yuasa1-3/+2
arch/mips/alchemy/devboards/prom.c: In function 'prom_init': arch/mips/alchemy/devboards/prom.c:60: error: ignoring return value of 'strict_strtoul', declared with attribute warn_unused_result Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/1761/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: Loongson: Add return value check for strict_strtoul()Wu Zhangjin1-2/+2
cc1: warnings being treated as errors arch/mips/loongson/common/env.c: In function 'prom_init_env': arch/mips/loongson/common/env.c:49: error: ignoring return value of 'strict_strtol', declared with attribute warn_unused_result arch/mips/loongson/common/env.c:50: error: ignoring return value of 'strict_strtol', declared with attribute warn_unused_result arch/mips/loongson/common/env.c:51: error: ignoring return value of 'strict_strtol', declared with attribute warn_unused_result arch/mips/loongson/common/env.c:52: error: ignoring return value of 'strict_strtol', declared with attribute warn_unused_result Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/1762/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: VPE loader: Check vmalloc return value in vpe_openJesper Juhl1-8/+6
The return value of the vmalloc() call in arch/mips/kernel/vpe.c::vpe_open() is not checked, so we potentially store a null pointer in v->pbuffer. Add a check for a null return and then return -ENOMEM in that case. [Ralf: The check added by Jesper's original patch is where it logically should be. Adding it eleminated the need for the checks in a few other places, so I removed them. There still is a zillion of other things that need to be fixed in this file / API.] Signed-off-by: Jesper Juhl <jj@chaosbits.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1747/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: compat: Don't clobber personality bits in 32-bit sys_personality().David Daney1-6/+7
If PER_LINUX32 has been set on a 32-bit kernel, only twiddle with the low-order personality bits, let the upper bits pass through. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: Camm Maguire <camm@maguirefamily.org> Patchwork: https://patchwork.linux-mips.org/patch/1751/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: Don't clobber personality high bits.David Daney1-2/+6
The high bits of current->personality carry settings that we don't want to clobber on each exec. Only clobber them if the lower bits that indicate either PER_LINUX or PER_LINUX32 are invalid. The clobbering prevents us from using useful bits like ADDR_NO_RANDOMIZE. Reported-by: Camm Maguire <camm@maguirefamily.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: Camm Maguire <camm@maguirefamily.org> Patchwork: https://patchwork.linux-mips.org/patch/1750/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: jz4740: Fix section mismatch in prom.cLars-Peter Clausen1-1/+1
This patch fixes the following section mismatch: WARNING: arch/mips/built-in.o(.text+0xc): Section mismatch in reference from the function jz4740_init_cmdline() to the variable .init.data:arcs_cmdline While were at it, make jz4740_init_cmdline static as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: jz4740: qi_lb60: Fix gpio for the 6th row of the keyboard matrixLars-Peter Clausen1-2/+2
This patch fixes the gpio number for the 6th row of the keyboard matrix. (And fixes a typo in my name...) Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: stable@kernel.org Signed-off-by: https://patchwork.linux-mips.org/patch/1754/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: Don't stomp on caller's ->regs[2] in copy_thread()Al Viro1-1/+0
We never needed that (->regs[2] is overwritten on return from syscall paths with return value of syscall, so storing it there early made no sense) and with new restart logics since d27240bf7e61d2656de18e158ec910a902030847 it has become really bad - we lose the original syscall number before the place where we decide that we might need a syscall restart. Note that for child we do need the assignment to regs[2] - it won't go through the normal return from syscall path. [Ralf: Issue found and reported by Lluís; initial investigations by me; bug finally found and patch by Al; testing by me and Lluís.] Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Tested-by: Lluís Batlle i Rossell <viriketo@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: Swarm: Fix typo in symbol name: RTC_M4LT81 -> RTC_M41T81Ralf Baechle1-4/+4
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-11-26perf, arch: Cleanup perf-pmu init vs lockup-detectorPeter Zijlstra1-1/+1
The perf hardware pmu got initialized at various points in the boot, some before early_initcall() some after (notably arch_initcall). The problem is that the NMI lockup detector is ran from early_initcall() and expects the hardware pmu to be present. Sanitize this by moving all architecture hardware pmu implementations to initialize at early_initcall() and move the lockup detector to an explicit initcall right after that. Cc: paulus <paulus@samba.org> Cc: davem <davem@davemloft.net> Cc: Michael Cree <mcree@orcon.net.nz> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1290707759.2145.119.camel@laptop> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-11-16suspend: constify platform_suspend_opsLionel Debroux3-3/+3
While at it, fix two checkpatch errors. Several non-const struct instances constified by this patch were added after the introduction of platform_suspend_ops in checkpatch.pl's list of "should be const" structs (79404849e90a41ea2109bd0e2f7c7164b0c4ce73). Patch against mainline. Inspired by hunks of the grsecurity patch, updated for newer kernels. Signed-off-by: Lionel Debroux <lionel_debroux@yahoo.fr> Acked-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-11-01tree-wide: fix comment/printk typosUwe Kleine-König8-9/+9
"gadget", "through", "command", "maintain", "maintain", "controller", "address", "between", "initiali[zs]e", "instead", "function", "select", "already", "equal", "access", "management", "hierarchy", "registration", "interest", "relative", "memory", "offset", "already", Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-10-30Merge git://git.infradead.org/mtd-2.6Linus Torvalds1-0/+97
* git://git.infradead.org/mtd-2.6: (82 commits) mtd: fix build error in m25p80.c mtd: Remove redundant mutex from mtd_blkdevs.c MTD: Fix wrong check register_blkdev return value Revert "mtd: cleanup Kconfig dependencies" mtd: cfi_cmdset_0002: make sector erase command variable mtd: cfi_cmdset_0002: add CFI detection for SST 38VF640x chips mtd: cfi_util: add support for switching SST 39VF640xB chips into QRY mode mtd: cfi_cmdset_0001: use defined value of P_ID_INTEL_PERFORMANCE instead of hardcoded one block2mtd: dubious assignment P4080/mtd: Fix the freescale lbc issue with 36bit mode P4080/eLBC: Make Freescale elbc interrupt common to elbc devices mtd: phram: use KBUILD_MODNAME mtd: OneNAND: S5PC110: Fix double call suspend & resume function mtd: nand: fix MTD_MODE_RAW writes jffs2: use kmemdup mtd: sm_ftl: cosmetic, use bool when possible mtd: r852: remove useless pci powerup/down from suspend/resume routines mtd: blktrans: fix a race vs kthread_stop mtd: blktrans: kill BKL mtd: allow to unload the mtdtrans module if its block devices aren't open ... Fix up trivial whitespace-introduced conflict in drivers/mtd/mtdchar.c
2010-10-30Merge branch 'master' of ↵David Woodhouse137-224/+468
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git Conflicts: drivers/mtd/mtd_blkdevs.c Merge Grant's device-tree bits so that we can apply the subsequent fixes. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2010-10-29ftrace/MIPS: Enable C Version of recordmcountWu Zhangjin1-0/+1
Selects HAVE_C_RECORDMCOUNT to use the C version of the recordmcount intead of the old Perl Version of recordmcount. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> LKML-Reference: <bb99009a9ac79d3f55a8c8bf1c8bd2bc0e1f160e.1288176026.git.wuzhangjin@gmail.com> Signed-off-by: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Make TASK_SIZE reflect proper size for both 32 and 64 bit processes.David Daney4-24/+37
The TASK_SIZE macro should reflect the size of a user process virtual address space. Previously for 64-bit kernels, this was not the case. The immediate cause of pain was in hugetlbfs/inode.c:hugetlb_get_unmapped_area() where 32-bit processes trying to mmap a huge page would be served a page with an address outside of the 32-bit address range. But there are other uses of TASK_SIZE in the kernel as well that would like an accurate value. The new definition is nice because it now makes TASK_SIZE and TASK_SIZE_OF() yield the same value for any given process. For 32-bit kernels there should be no change, although I did factor out some code in asm/processor.h that became identical for the 32-bit and 64-bit cases. __UA_LIMIT is now set to ~((1 << SEGBITS) - 1) for 64-bit kernels. This should eliminate the possibility of getting a AddressErrorException in the kernel for addresses that pass the access_ok() test. With the patch applied, I can still run o32, n32 and n64 processes, and have an o32 shell fork/exec both n32 and n64 processes. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1701/
2010-10-29MIPS: Allow UserLocal on MIPS_R1 processorsKevin Cernekee1-6/+7
Some MIPS32R1 processors implement UserLocal (RDHWR $29) to accelerate programs that make extensive use of thread-local storage. Therefore, setting up the HWRENA register should not depend on cpu_has_mips_r2. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
2010-10-29MIPS: Honor L2 bypass bitKevin Cernekee1-4/+30
On many of the newer MIPS32 cores, CP0 CONFIG2 bit 12 (L2B) indicates that the L2 cache is disabled and therefore Linux should not attempt to use it. [Ralf: Moved the code added by Kevin's original patch into a separate function that can easily be replaced for platforms that need more a different probe.] Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org> Cc: <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/1723/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Add BMIPS CP0 register definitionsKevin Cernekee1-0/+51
Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: mbizon@freebox.fr Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Tested-by: Florian Fainelli <ffainelli@freebox.fr> Patchwork: https://patchwork.linux-mips.org/patch/1708/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
2010-10-29MIPS: Add BMIPS processor types to KconfigKevin Cernekee1-0/+63
[v2: add "VIPER" marketing name for BMIPS4350] Add processor feature definitions for BMIPS3300, BMIPS4350, BMIPS4380, and BMIPS5000. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: mbizon@freebox.fr Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Tested-by: Florian Fainelli <ffainelli@freebox.fr> Patchwork: https://patchwork.linux-mips.org/patch/1716/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
2010-10-29MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC codeKevin Cernekee4-61/+65
BMIPS processor cores are used in 50+ different chipsets spread across 5+ product lines. In many cases the chipsets do not share the same peripheral register layouts, the same register blocks, the same interrupt controllers, the same memory maps, or much of anything else. But, across radically different SoCs that share nothing more than the same BMIPS CPU, a few things are still mostly constant: SMP operations Access to performance counters DMA cache coherency quirks Cache and memory bus configuration So, it makes sense to treat each BMIPS processor type as a generic "building block," rather than tying it to a specific SoC. This makes it easier to support a large number of BMIPS-based chipsets without unnecessary duplication of code, and provides the infrastructure needed to support BMIPS-proprietary features. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: mbizon@freebox.fr Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Tested-by: Florian Fainelli <ffainelli@freebox.fr> Patchwork: https://patchwork.linux-mips.org/patch/1706/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
2010-10-29MIPS: Add support for hardware performance events (mipsxx)Deng-Cheng Zhu2-0/+1059
This patch adds the mipsxx Perf-events support based on the skeleton. Generic hardware events and cache events are now fully implemented for the 24K/34K/74K/1004K cores. To support other cores in mipsxx (such as R10000/SB1), the generic hardware event tables and cache event tables need to be filled out. To support other CPUs which have different PMU than mipsxx, such as RM9000 and LOONGSON2, the additional files perf_event_$cpu.c need to be created. Raw event is an important part of Perf-events. It helps the user collect performance data for events that are not listed as the generic hardware events and cache events but ARE supported by the CPU's PMU. This patch also adds this feature for mipsxx 24K/34K/74K/1004K. For how to use it, please refer to processor core software user's manual and the comments for mipsxx_pmu_map_raw_event() for more details. Please note that this is a "precise" implementation, which means the kernel will check whether the requested raw events are supported by this CPU and which hardware counters can be assigned for them. To test the functionality of Perf-event, you may want to compile the tool "perf" for your MIPS platform. You can refer to the following URL: http://www.linux-mips.org/archives/linux-mips/2010-10/msg00126.html You also need to customize the CFLAGS and LDFLAGS in tools/perf/Makefile for your libs, includes, etc. In case you encounter the boot failure in SMVP kernel on multi-threading CPUs, you may take a look at: http://www.linux-mips.org/git?p=linux-mti.git;a=commitdiff;h=5460815027d802697b879644c74f0e8365254020 Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Cc: ddaney@caviumnetworks.com Cc: matt@console-pimps.org Patchwork: https://patchwork.linux-mips.org/patch/1689/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/kernel/perf_event_mipsxx.c
2010-10-29MIPS: Perf-events: Add callchain supportDeng-Cheng Zhu1-1/+107
Adds callchain support for MIPS Perf-events. For more info on this feature, please refer to tools/perf/Documentation/perf-report.txt and tools/perf/design.txt. Currently userspace callchain data is not recorded, because we do not have a safe way to do this. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> Acked-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Cc: matt@console-pimps.org Patchwork: https://patchwork.linux-mips.org/patch/1690/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: add support for hardware performance events (skeleton)Deng-Cheng Zhu4-0/+523
This patch provides the skeleton of the HW perf event support. To enable this feature, we can not choose the SMTC kernel; Oprofile should be disabled; kernel performance events be selected. Then we can enable it in Kernel type menu. Oprofile for MIPS platforms initializes irq at arch init time. Currently we do not change this logic to allow PMU reservation. If a platform has EIC, we can use the irq base and perf counter irq offset defines for the interrupt controller in specific init_hw_perf_events(). Based on this skeleton patch, the 3 different kinds of MIPS PMU, namely, mipsxx/loongson2/rm9000, can be supported by adding corresponding lower level C files at the bottom. The suggested names of these files are perf_event_mipsxx.c/perf_event_loongson2.c/perf_event_rm9000.c. So, for example, we can do this by adding "#include perf_event_mipsxx.c" at the bottom of perf_event.c. In addition, PMUs with 64bit counters are also considered in this patch. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Cc: ddaney@caviumnetworks.com Cc: matt@console-pimps.org Patchwork: https://patchwork.linux-mips.org/patch/1688/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: add support for software performance eventsDeng-Cheng Zhu5-5/+36
Software events are required as part of the measurable stuff by the Linux performance counter subsystem. Here is the list of events added by this patch: PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_ALIGNMENT_FAULTS PERF_COUNT_SW_EMULATION_FAULTS Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Acked-by: David Daney <ddaney@caviumnetworks.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Patchwork: https://patchwork.linux-mips.org/patch/1686/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: define local_xchg from xchg_local to atomic_long_xchgDeng-Cheng Zhu1-1/+1
Perf-events is now using local_t helper functions internally. There is a use of local_xchg(). On MIPS, this is defined to xchg_local() which is missing in asm/system.h. This patch re-defines local_xchg() in asm/local.h to atomic_long_xchg(). Then Perf-events can pass the build. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Cc: ddaney@caviumnetworks.com Cc: matt@console-pimps.org Patchwork: https://patchwork.linux-mips.org/patch/1687/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: AR7: Add support for Titan (TNETV10xx) SoC variantFlorian Fainelli5-13/+345
Add support for Titan TNETV1050,1055,1056,1060 variants. This SoC is almost completely identical to AR7 except on a few points: - a second bank of gpios is available - vlynq0 on titan is vlynq1 on ar7 - different PHY addresses for cpmac0 This SoC can be found on commercial products like the Linksys WRTP54G Original patch by Xin with improvments by Florian. Signed-off-by: Xin Zhen <xlonestar2000@aim.com> Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/1563/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2010-10-29MIPS: AR7: Initialize GPIO earlierFlorian Fainelli3-2/+5
In order to detect the Titan variant, we must initialize GPIOs earlier since detection relies on some GPIO values to be set. Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/1562/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2010-10-29MIPS: Add platform device and Kconfig for Octeon USB EHCI / OHCIDavid Daney2-1/+106
Declare that OCTEON reference boards have both OHCI and EHCI. Add platform devices for the corresponding hardware. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-usb@vger.kernel.org To: dbrownell@users.sourceforge.net Patchwork: http://patchwork.linux-mips.org/patch/1676/ Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Add register definitions for EHCI / OHCI USB glue logic.David Daney1-0/+261
The EHCI and OHCI blocks connection to the I/O bus is controlled by these registers. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-usb@vger.kernel.org To: dbrownell@users.sourceforge.net Patchwork: http://patchwork.linux-mips.org/patch/1674/ Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
2010-10-29MIPS: Octeon: Apply CN63XXP1 errata workarounds.David Daney4-5/+69
The CN63XXP1 needs a couple of workarounds to ensure memory is not written in unexpected ways. All PREF with hints in the range 0-4,6-24 are replaced with PREF 28. We pass a flag to the assembler to cover compiler generated code, and patch uasm for the dynamically generated code. The write buffer threshold is reduced to 4. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1672/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Use I/O clock rate for calculations.David Daney2-2/+2
The I2C and UARTS are clocked by the I/O clock, use its rate for these devices. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1670/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Add octeon_get_io_clock_rate() for cn63xxDavid Daney2-28/+49
Starting with cn63xx Octeon I/O blocks are clocked at a different rate than the CPU. Add a new function octeon_get_io_clock_rate() that yields the I/O clock rate. Also rearrange octeon_get_clock_rate() to get the value from the saved sysinfo structure. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1671/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Remove bogus code from octeon_get_clock_rate()David Daney1-2/+0
We can run with any simulator clock rate. Get rid of the code overriding it to 6MHz. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1669/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Scale Octeon2 clocks in octeon_init_cvmcount()David Daney1-3/+31
The per-CPU clocks are synchronized from IPD_CLK_COUNT, on cn63XX it must be scaled by the clock frequency ratio. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1667/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Enable Read Inhibit / eXecute Inhibit on Octeon II.David Daney1-1/+1
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1666/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Probe for Octeon II CPUs.David Daney1-0/+7
The OCTEON II ISA extends the original OCTEON ISA, so give it its own __elf_platform string so optimized libraries can be selected in userspace. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1665/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Handle Octeon II caches.David Daney1-1/+15
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1664/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Add identifiers for Octeon II CPUs.David Daney1-1/+2
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1662/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Update L2 Cache code for CN63XXDavid Daney3-417/+629
The CN63XX has a different L2 cache architecture. Update the helper functions to reflect this. Some joining of split lines was also done to improve readability, as well as reformatting of comments. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1663/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Add cn63XX to Octeon chip detection macros.David Daney1-8/+28
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1661/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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