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2015-09-16genirq: Remove irq argument from irq flow handlersThomas Gleixner1-2/+2
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
2015-09-10dma-mapping: consolidate dma_{alloc,free}_{attrs,coherent}Christoph Hellwig1-10/+0
Since 2009 we have a nice asm-generic header implementing lots of DMA API functions for architectures using struct dma_map_ops, but unfortunately it's still missing a lot of APIs that all architectures still have to duplicate. This series consolidates the remaining functions, although we still need arch opt outs for two of them as a few architectures have very non-standard implementations. This patch (of 5): The coherent DMA allocator works the same over all architectures supporting dma_map operations. This patch consolidates them and converges the minor differences: - the debug_dma helpers are now called from all architectures, including those that were previously missing them - dma_alloc_from_coherent and dma_release_from_coherent are now always called from the generic alloc/free routines instead of the ops dma-mapping-common.h always includes dma-coherent.h to get the defintions for them, or the stubs if the architecture doesn't support this feature - checks for ->alloc / ->free presence are removed. There is only one magic instead of dma_map_ops without them (mic_dma_ops) and that one is x86 only anyway. Besides that only x86 needs special treatment to replace a default devices if none is passed and tweak the gfp_flags. An optional arch hook is provided for that. [linux@roeck-us.net: fix build] [jcmvbkbc@gmail.com: fix xtensa] Signed-off-by: Christoph Hellwig <hch@lst.de> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Michal Simek <monstr@monstr.eu> Cc: Jonas Bonn <jonas@southpole.se> Cc: Chris Metcalf <cmetcalf@ezchip.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2015-09-03MIPS: Netlogic: Use chip_data for irq_chip methodsKamlakant Patel1-6/+6
Update mips/netlogic/common/irq.c and mips/pci/msi-xlp.c to use chip_data to store interrupt controller data pointer. It uses handler_data now, and that causes errors when an API (like the GPIO subsystem) tries to use the handler data. Signed-off-by: Kamlakant Patel <kamlakant.patel@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10817/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-08-26MIPS: netlogic: Prepare ipi handlers for irq argument removalThomas Gleixner1-2/+4
The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/10705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-08-03MIPS: SMP: Don't increment irq_count multiple times for call function IPIsAlex Smith1-1/+1
The majority of SMP platforms handle their IPIs through do_IRQ() which calls irq_{enter/exit}(). When a call function IPI is received, smp_call_function_interrupt() is called which also calls irq_{enter,exit}(), meaning irq_count is raised twice. When tick broadcasting is used (which is implemented via a call function IPI), this incorrectly causes all CPU idle time on the core receiving broadcast ticks to be accounted as time spent servicing IRQs, as account_process_tick() will account as such if irq_count is greater than 1. This results in 100% CPU usage being reported on a core which receives its ticks via broadcast. This patch removes the SMP smp_call_function_interrupt() wrapper which calls irq_{enter,exit}(). Platforms which handle their IPIs through do_IRQ() now call generic_smp_call_function_interrupt() directly to avoid incrementing irq_count a second time. Platforms which don't (loongson, sgi-ip27, sibyte) call generic_smp_call_function_interrupt() wrapped in irq_{enter,exit}(). Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10770/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-08MIPS: Netlogic: Fix double inclusion of <asm/netlogic/common.h>.Ralf Baechle1-1/+0
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-01MIPS: Netlogic: Do not enable SUE for coreJayachandran C1-1/+1
Enabling the SUE bit for core can can result in rare cache errors which are difficult to track down, so do not enable it. This can cause a minor performance loss in some tests. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-01MIPS: Netlogic: Handle XLP hardware errataJayachandran C1-0/+20
Core configuration register IFU_BRUB_RESERVE has to be setup to handle a silicon errata which can result in a CPU hang. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8902/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-01MIPS: Netlogic: Move cores per node out of multi-node.hJayachandran C2-17/+19
Use the current_cpu_data package field to get the node of the current CPU. This allows us to remove xlp_cores_per_node and move nlm_threads_per_node() and nlm_cores_per_node() to netlogic/common.h, which simplifies code. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8889/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-01MIPS: Netlogic: Use MIPS topology.hJayachandran C1-0/+1
commit bda4584cd943 ("MIPS: Support CPU topology files in sysfs") added topology related macros for all MIPS platforms and commit bbbf6d8768f5 ("MIPS: NL: Fix nlm_xlp_defconfig build error") removed most of the contents from mach-netlogic/topology.h. The netlogic specific topology is not needed anymore, we just need to setup the package field in current_cpu_data. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8888/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-02-13mips: use %*pb[l] to print bitmaps including cpumasks and nodemasksTejun Heo1-8/+5
printk and friends can now format bitmaps using '%*pb[l]'. cpumask and nodemask also provide cpumask_pr_args() and nodemask_pr_args() respectively which can be used to generate the two printf arguments necessary to format the specified cpu/nodemask. Signed-off-by: Tejun Heo <tj@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-05-30MIPS: Netlogic: Add support for XLP5XXYonghong Song1-0/+4
Add support for the XLP5XX processor which is an 8 core variant of the XLP9XX. Add XLP5XX cases to code which earlier handled XLP9XX. Signed-off-by: Yonghong Song <ysong@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6871/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-30MIPS: Netlogic: PIC freq calculation for XLP 9XX/2XXGanesan Ramalingam1-1/+4
Update PIC frequency calculation for XLP9XX and 2XX processors using the correct PLL registers. This should work for all possible board configurations. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6876/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-30MIPS: Netlogic: Use PRID_IMP_MASK macroJayachandran C1-2/+3
Use PRID_IMP_MASK macro instead of 0xff00 to extract the processor type. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6868/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-30MIPS: Netlogic: Enable access to more than 64GBJayachandran C1-0/+15
The ELPA bit needs to be set in the PAGEGRAIN register to enable access to >64GB physical address. Update reset.S to do this from every hardware thread. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6866/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-30MIPS: Netlogic: Reduce size of reset codeJayachandran C2-11/+16
Update thread wakeup function to use scratch registers for saving SP and RA. Move the register restore code needed for thread 0 to the calling function. This reduces the size of code copied to the reset vector. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6910/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-30MIPS: Netlogic: Use cpumask_scnprintf for wakeup_maskJayachandran C1-3/+4
Use standard function to print cpumask. Also fixup a typo in the same file. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: g@linux-mips.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6909/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-30MIPS: Netlogic: Warn on invalid irqJayachandran C1-0/+2
Warn and return if invalid IRQ is passed to nlm_set_pic_extra_ack. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6862/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-27MIPS: SMP: Remove plat_smp_ops cpus_done method.Ralf Baechle1-5/+0
Nothing was using the method and there isn't any need for this hook. This leaves smp_cpus_done() empty for the moment. As suggested by Paul Bolle <pebolle@tiscali.nl>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-24mips: delete non-required instances of include <linux/init.h>Paul Gortmaker2-2/+0
None of these files are actually using any __init type directives and hence don't need to include <linux/init.h>. Most are just a left over from __devinit and __cpuinit removal, or simply due to code getting copied from one driver to the next. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6320/
2014-01-24MIPS: Netlogic: XLP9XX PIC OF supportJayachandran C1-6/+31
Support for adding legacy IRQ domain for XLP9XX. The node id of the PIC has to be calulated differently for XLP9XX. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6286/
2014-01-24MIPS: Netlogic: Add cpu to node mapping for XLP9XXJayachandran C2-6/+8
XLP9XX has 20 cores per node, opposed to 8 on earlier XLP8XX. Update code that calculates node id from cpu id to handle this. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6283/
2014-01-24MIPS: Netlogic: XLP9XX UART offsetJayachandran C1-0/+2
Update IO offset of the early console UART. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6281/
2014-01-24MIPS: Netlogic: SYS block updates of XLP9XXJayachandran C1-0/+8
Add the SYS block registers for XLP9XX, most of them have changed. The wakeup sequence has been updated to set the coherent mode from the main thread rather than the woken up thread. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6280/
2014-01-24MIPS: Netlogic: L1D cacheflush before thread enable on XLPIIYonghong Song1-2/+23
On XLPII CPUs, the L1D cache has to be flushed with regular cache operations before enabling threads in a core. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6276/
2014-01-24MIPS: Netlogic: Some cleanups for assembly codeJayachandran C2-15/+17
No change in logic, the changes are: * cleanup some whitespace and comments * remove confusing argument of SYS_CPU_COHERENT_BASE macro * make the numerical labels in macros consistent Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6273/
2014-01-24MIPS: Netlogic: Add MSI support for XLPJayachandran C1-8/+21
Add MSI chip and MSIX chip definitions. For MSI, we map the link interrupt to a MSI link IRQ which will do a second level of dispatch based on the MSI status register. The MSI chip definitions use the MSI enable register to enable and disable the MSI irqs. For MSI-X, we split the 32 available MSI-X vectors across the four PCIe links (8 each). These PIC interrupts generate an IRQ per link which uses a second level dispatch as well. The MSI-X chip definition uses the standard functions to enable and disable interrupts. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6270/
2013-10-29MIPS: Panic messages should not end in \n.Ralf Baechle1-1/+1
Panic() is going to add a \n itself and it's annoying if a panic message rolls of the screen on a device with no scrollback. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-09-03MIPS: Netlogic: XLP2XX CPU and PIC frequencyGanesan Ramalingam1-1/+2
Add code to calculate the CPU and PIC frequency for XLP2XX SoCs. Since the PIC frequency on XLP2XX can be configured, add a new macro pic_timer_freq() to be used in netlogic/common/time.c. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: Ganesan Ramalingam <ganesanr@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/5701/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-09-03MIPS: Netlogic: Call xlp_mmu_init on all threadsJayachandran C1-3/+1
The config7/config4 register has to be written on all the threads. This does not cause any problems in XLP, but is needed for XLPII Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-19Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds1-11/+57
Pull MIPS fixes from Ralf Baechle: "MIPS fixes for 3.11. Half of then is for Netlogic the remainder touches things across arch/mips. Nothing really dramatic and by rc1 standards MIPS will be in fairly good shape with this applied. Tested by building all MIPS defconfigs of which with this pull request four platforms won't build. And yes, it boots also on my favorite test systems" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: kvm: Kconfig: Drop HAVE_KVM dependency from VIRTUALIZATION MIPS: Octeon: Fix DT pruning bug with pip ports MIPS: KVM: Mark KVM_GUEST (T&E KVM) as BROKEN_ON_SMP MIPS: tlbex: fix broken build in v3.11-rc1 MIPS: Netlogic: Add XLP PIC irqdomain MIPS: Netlogic: Fix USB block's coherent DMA mask MIPS: tlbex: Fix typo in r3000 tlb store handler MIPS: BMIPS: Fix thinko to release slave TP from reset MIPS: Delete dead invocation of exception_exit().
2013-07-19MIPS: Netlogic: Add XLP PIC irqdomainJayachandran C1-11/+57
Add a legacy irq domain for the XLP PIC interrupts. This will be used when interrupts are assigned from the device tree. This change is required after commit c5cdc67 "irqdomain: Remove temporary MIPS workaround code". Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: Jayachandran C <jchandra@broadcom.com> Patchwork: https://patchwork.linux-mips.org/patch/5597/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-14MIPS: Delete __cpuinit/__CPUINIT usage from MIPS codePaul Gortmaker3-7/+3
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream. The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. Here, we remove all the MIPS __cpuinit from C code and __CPUINIT from asm files. MIPS is interesting in this respect, because there are also uasm users hiding behind their own renamed versions of the __cpuinit macros. [1] https://lkml.org/lkml/2013/5/20/589 [ralf@linux-mips.org: Folded in Paul's followup fix.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5494/ Patchwork: https://patchwork.linux-mips.org/patch/5495/ Patchwork: https://patchwork.linux-mips.org/patch/5509/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-13MIPS: Netlogic: Fix plat_irq_dispatchJayachandran C1-4/+3
Fix an issue in plat_irq_dispatch due to which it can call do_IRQ with a PIC irq that is not mapped. When a per-cpu interrupt and a PIC interrupt are both active, the check 'eirr & PERCPU_IRQ_MASK' will be true, but the interrupt in 'i' will be the number of the PIC interrupt. In this case, we will call do_IRQ on the PIC interrupt without mapping it with nlm_irq_to_xirq(). Fix this by using __ffs64 instead of __ilog2_u64 and using the interrupt number instead of mask to identify per-cpu interrupts. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-13MIPS: Netlogic: Remove workarounds for early SoCsJayachandran C1-22/+1
The XLPs in production do not need these workarounds. Remove the code and the associated ifdef. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5430/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-13MIPS: Netlogic: use branch instead of jumpJayachandran C2-2/+2
Fix an issue in the reset code. Since this code is copied to the reset vector, using 'j' for looping is not correct. Use relative branch 'b'. Update the usage of 'j' in smpboot.S to be consistent although it is not a bug there. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5427/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-13MIPS: Netlogic: move cpu_ready array to boot areaJayachandran C3-7/+10
Move the nlm_cpu_ready[] array used by the cpu wakeup code to the boot area, along with rest of the boot parameter code. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5425/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-13MIPS: Netlogic: Add nlm_get_boot_data() helperJayachandran C1-3/+3
This moves the calculation and casting needed to access the CPU initialization data to a function nlm_get_boot_data() Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5426/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-13MIPS: Netlogic: Initialization when !CONFIG_SMPJayachandran C2-7/+2
The core initialization and reset vector setup needs to be done even when booting uniprocessor. Move this code from smp.c to setup.c Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5428/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-13MIPS: Netlogic: Split reset code out of smpboot.SJayachandran C3-187/+251
The reset and core initialization code should be available for uniprocessor as well. This changes is just to take out the code into a different file, without any change to the logic. The change for uniprocessor initialization code is in a later patch. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5423/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-13MIPS: Netlogic: SWIOTLB dma ops for 32-bit DMAGanesan Ramalingam2-0/+108
Add SWIOTLB config option and related files to Netlogic platform. Some XLP SoC components like the SD/MMC interface cannot do DMA beyond 32-bit physical address. The SD/MMC driver can use memory outside this range for IO, to support this we have to add bounce buffers implemented by SWIOTLB. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: Ganesan Ramalingam <ganesanr@broadcom.com> Patchwork: https://patchwork.linux-mips.org/patch/5410/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08MIPS: Netlogic: print cpumask with cpumask_scnprintfJayachandran C1-9/+12
Use standard function to print cpumask. Also fixup the name of the variable used and make it static. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/5024/ Acked-by: John Crispin <blogic@openwrt.org>
2013-02-21Merge branch 'mips-next-3.9' of ↵Ralf Baechle4-29/+82
git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
2013-02-17MIPS: Netlogic: use preset loops per jiffyJayachandran C1-0/+4
Doing calibrate delay on a hardware thread will be inaccurate since it depends on the load on other threads in the core. It will also slow down the boot process when done for 128 hardware threads. Switch to a pre-computed loops per jiffy based on the core frequency. The value is computed based on the core frequency and roughly matches the value calculated by calibrate_delay(). Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4791/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Use PIC timer as a clocksourceJayachandran C2-1/+53
The XLR/XLS/XLP PIC has a 8 countdown timers which run at the PIC frequencey. One of these can be used as a clocksource to provide timestamps that is common across cores. This can be used in place of the count/compare clocksource which is per-CPU. On XLR/XLS PIC registers are 32-bit, so we just use the lower 32-bits of the PIC counter. On XLP, the whole 64-bit can be used. Provide common macros and functions for PIC timer registers on XLR/XLS and XLP, and use them to register a PIC clocksource. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4786/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Split XLP L1 i-cache among threadsJayachandran C1-0/+6
Since we now use r4k cache code for Netlogic XLP, it is better to split L1 icache among the active threads, so that threads won't step on each other while flushing icache. The L1 dcache is already split among the threads in the core. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4787/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Optimize EIMR/EIRR accesses in 32-bitJayachandran C2-28/+19
Provide functions ack_c0_eirr(), set_c0_eimr(), clear_c0_eimr() and read_c0_eirr_and_eimr() that do the EIMR and EIRR operations and update the interrupt handling code to use these functions. Also, use the EIMR register functions to mask interrupts in the irq code. The 64-bit interrupt request and mask registers (EIRR and EIMR) are accessed when the interrupts are off, and the common operations are to set or clear a bit in these registers. Using the 64-bit c0 access functions for these operations is not optimal in 32-bit, because it will disable/restore interrupts and split/join the 64-bit value during each register access. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4790/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle2-9/+9
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-11-09MIPS: Netlogic: Support for XLR/XLS Fast Message NetworkGanesan Ramalingam2-5/+7
On XLR/XLS, the cpu cores communicate with fast on-chip devices (e.g. network accelerator, security engine etc.) using the Fast Messaging Network(FMN). The FMN queues and credits needs to be configured and intialized before it can be used. The co-processor 2 on XLR/XLS CPU cores has registers for FMN access, and the XLR/XLS has custom instructions for sending and loading messages. The FMN can deliver also per-cpu interrupts when messages are available at the CPU. This patch adds FMN initialization, adds interrupt setup and handling, and also provides support for sending and receiving FMN messages. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4468 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09MIPS: Netlogic: PIC IRQ handling update for multi-chipJayachandran C2-75/+102
Create struct nlm_pic_irq for interrupts handled by the PIC. This simplifies IRQ handling for multi-SoC as well as the single SoC cases. Also split the setup of percpu and PIC interrupts so that we can configure the PIC interrupts for every node. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4467 Signed-off-by: John Crispin <blogic@openwrt.org>
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