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2006-03-21[MIPS] TX49XX has prefetch.Atsushi Nemoto2-2/+9
2006-03-21[MIPS] Kill tlb-andes.c.Thiemo Seufer3-260/+6
2006-03-21[MIPS] War on whitespace: cleanup initial spaces followed by tabs.Ralf Baechle1-9/+9
2006-03-21[MIPS] Remove CONFIG_BUILD_ELF64.Ralf Baechle1-13/+0
2006-03-21[MIPS] sc-rm7k.c cleanupAtsushi Nemoto1-16/+9
2006-03-18[MIPS] local_r4k_flush_cache_page fixAtsushi Nemoto2-5/+9
2006-03-09[MIPS] Scatter a bunch of __init over tlbex.c.Ralf Baechle1-17/+17
2006-02-28[MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.Ralf Baechle1-5/+11
2006-02-21[MIPS] Sibyte: #if CONFIG_* doesn't fly.Ralf Baechle1-1/+1
2006-02-14[MIPS] Add protected_blast_icache_range, blast_icache_range, etc.Atsushi Nemoto2-151/+23
2006-02-07[MIPS] Support /proc/kcore for MIPSDaniel Jacobowitz1-0/+16
2006-02-07[MIPS] Remove wrong __user tags.Atsushi Nemoto2-7/+5
2006-01-10MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle1-2/+2
2005-12-12[PATCH] mips: setup_zero_pages count 1Hugh Dickins1-2/+2
2005-12-01[MIPS] Use reset_page_mapcount to initialize empty_zero_page usage counter.Ralf Baechle1-1/+1
2005-10-29[PATCH] mm: init_mm without ptlockHugh Dickins1-3/+1
2005-10-29SB1 cache exception handling.Andrew Isaacson2-8/+51
2005-10-29Add support for SB1A CPU.Andrew Isaacson1-0/+1
2005-10-29Fix zero length sys_cacheflushAtsushi Nemoto1-0/+2
2005-10-29Rename page argument of flush_cache_page to something more descriptive.Ralf Baechle1-16/+17
2005-10-29Fix wrong comment.Ralf Baechle1-1/+1
2005-10-29Fixup a few lose ends in explicit support for MIPS R1/R2.Ralf Baechle1-2/+2
2005-10-29Don't copy SB1 cache error handler to uncached memory.Ralf Baechle1-1/+0
2005-10-29Fix stale comment in c-sb1.c.Andrew Isaacson1-1/+1
2005-10-29Cleanup the mess in cpu_cache_init.Ralf Baechle5-54/+44
2005-10-29Use R4000 TLB routines for SB1 also.Ralf Baechle2-386/+1
2005-10-29Sync c-tx39.c with c-r4k.c.Atsushi Nemoto1-4/+5
2005-10-29Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer2-1/+2
2005-10-29Minor code cleanup.Thiemo Seufer1-15/+15
2005-10-29R4600 v2.0 needs a nop before tlbp.Thiemo Seufer1-0/+2
2005-10-29Don't set up a sg dma address if we have no page address for some reason.Thiemo Seufer1-38/+8
2005-10-29More .set push/pop.Thiemo Seufer1-2/+2
2005-10-29Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer2-7/+10
2005-10-29Handle mtc0 - tlb write hazard for VR5432.Ralf Baechle1-0/+1
2005-10-29Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle4-29/+13
2005-10-29Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov1-0/+1
2005-10-29More AP / SP bits for the 34K, the Malta bits and things. Still wantsRalf Baechle2-5/+3
2005-10-29Mark a few variables __read_mostly.Ralf Baechle1-1/+7
2005-10-29MIPS R2 instruction hazard handling.Ralf Baechle1-0/+1
2005-10-29Detect the 34K.Ralf Baechle1-0/+1
2005-10-29Define kmap_atomic_pfn() for MIPS.Ralf Baechle1-0/+19
2005-10-29Date: Fri Jul 8 20:10:17 2005 +0000Ralf Baechle1-1/+1
2005-10-29Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.Ralf Baechle4-6/+6
2005-10-29Avoid tlbw* hazards for the R4600/R4700/R5000.Maciej W. Rozycki1-1/+6
2005-10-29Inline ioremap() calls for constant addresses that map to KSEG1.Maciej W. Rozycki1-12/+3
2005-10-29Fix the diagnostic dump for the XTLB refill handler.Maciej W. Rozycki1-1/+8
2005-10-29Fix a diagnostic message.Maciej W. Rozycki1-1/+1
2005-10-29Use macros for the RM7k cp0.config bits instead of magic numbers.Maciej W. Rozycki1-9/+9
2005-10-29Optimize R3k TLB Load/Store/Modified handlers, by schedulingMaciej W. Rozycki1-40/+30
2005-10-29Fill R3k load delay slots properly.Maciej W. Rozycki1-0/+3
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