linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Collapse)	Author	Files	Lines
2010-10-29	MIPS: Honor L2 bypass bit	Kevin Cernekee	1	-4/+30
	On many of the newer MIPS32 cores, CP0 CONFIG2 bit 12 (L2B) indicates that the L2 cache is disabled and therefore Linux should not attempt to use it. [Ralf: Moved the code added by Kevin's original patch into a separate function that can easily be replaced for platforms that need more a different probe.] Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org> Cc: <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/1723/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-30	MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.	Kevin Cernekee	1	-0/+5
	This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover MIPSxx-style board cache code. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-03-12	[MIPS] Fix loads of section missmatches	Ralf Baechle	1	-2/+1
	Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11	[MIPS] Fix "no space between function name and open parenthesis" warnings.	Ralf Baechle	1	-1/+1
	Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29	[MIPS] MIPS32/MIPS64 S-cache fix and cleanup	Atsushi Nemoto	1	-32/+3
	Use blast_scache_range, blast_inv_scache_range for mips32/mips64 scache routine. Also initialize waybit for MIPS32/MIPS64 S-cache. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29	[MIPS] MIPS32/MIPS64 secondary cache management	Chris Dearman	1	-0/+141
	Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>