summaryrefslogtreecommitdiffstats
path: root/arch/mips/mm/c-tx39.c
AgeCommit message (Expand)AuthorFilesLines
2008-09-05[MIPS] TX39xx: Add missing local_flush_icache_range initializationAtsushi Nemoto1-0/+1
2008-09-05[MIPS] Fix WARNING: at kernel/smp.c:290Thomas Bogendoerfer1-0/+1
2008-04-07[MIPS] Handle aliases in vmalloc correctly.Ralf Baechle1-0/+15
2008-03-12[MIPS] Fix loads of section missmatchesRalf Baechle1-1/+1
2007-10-11[MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle1-3/+3
2007-03-07[MIPS] TX39: Remove redundant tx39_blast_icache() callsAtsushi Nemoto1-12/+6
2006-10-01[MIPS] Remove __flush_icache_pageAtsushi Nemoto1-29/+0
2006-09-27[MIPS] Retire flush_icache_page from mm use.Ralf Baechle1-2/+2
2006-04-19[MIPS] Handle IDE PIO cache aliases on SMP.Ralf Baechle1-0/+7
2006-03-18[MIPS] local_r4k_flush_cache_page fixAtsushi Nemoto1-1/+0
2006-02-14[MIPS] Add protected_blast_icache_range, blast_icache_range, etc.Atsushi Nemoto1-61/+9
2005-10-29Cleanup the mess in cpu_cache_init.Ralf Baechle1-1/+1
2005-10-29Sync c-tx39.c with c-r4k.c.Atsushi Nemoto1-4/+5
2005-10-29Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle1-0/+1
2005-10-29Update MIPS to use the 4-level pagetable code thereby getting rid ofRalf Baechle1-1/+3
2005-04-16Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds1-0/+493
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 05:05:13 +0000