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2011-12-07MIPS: BMIPS: Add set/clear CP0 macros for BMIPS operationsKevin Cernekee1-1/+8
Several BMIPS-specific CP0 registers are used for SMP boot and other operations. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2956/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-10-24MIPS: Add accessor macros for 64-bit performance counter registers.David Daney1-0/+8
Signed-off-by: David Daney <david.daney@cavium.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2789/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-03-31Fix common misspellingsLucas De Marchi1-2/+2
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
2010-10-29MIPS: Add BMIPS CP0 register definitionsKevin Cernekee1-0/+51
Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: mbizon@freebox.fr Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Tested-by: Florian Fainelli <ffainelli@freebox.fr> Patchwork: https://patchwork.linux-mips.org/patch/1708/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
2010-08-05MIPS: Define ST0_NMI in asm/mipsregs.hDavid Daney1-0/+1
This is used by the forthcoming OCTEON watchdog patch. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: wim@iguana.be Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1498/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-15 MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1Shane McDonald1-1/+8
In the FPU emulator code of the MIPS, the Cause bits of the FCSR register are not currently writeable by the ctc1 instruction. In odd corner cases, this can cause problems. For example, a case existed where a divide-by-zero exception was generated by the FPU, and the signal handler attempted to restore the FPU registers to their state before the exception occurred. In this particular setup, writing the old value to the FCSR register would cause another divide-by-zero exception to occur immediately. The solution is to change the ctc1 instruction emulator code to allow the Cause bits of the FCSR register to be writeable. This is the behaviour of the hardware that the code is emulating. This problem was found by Shane McDonald, but the credit for the fix goes to Kevin Kissell. In Kevin's words: I submit that the bug is indeed in that ctc_op: case of the emulator. The Cause bits (17:12) are supposed to be writable by that instruction, but the CTC1 emulation won't let them be updated by the instruction. I think that actually if you just completely removed lines 387-388 [...] things would work a good deal better. At least, it would be a more accurate emulation of the architecturally defined FPU. If I wanted to be really, really pedantic (which I sometimes do), I'd also protect the reserved bits that aren't necessarily writable. Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com> To: anemo@mba.ocn.ne.jp To: kevink@paralogos.com To: sshtylyov@mvista.com Patchwork: http://patchwork.linux-mips.org/patch/1205/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2010-02-27MIPS: Add accessor functions and bit definitions for c0_PageGrainDavid Daney1-0/+11
Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/950/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27MIPS: Decode c0_config4 for large TLBs.David Daney1-0/+4
For processors that have more than 64 TLBs, we need to decode both config1 and config4 to determine the total number TLBs. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/866/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-01-28MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQsDavid VomLehn1-0/+12
The MIPS processor is limited to 64 external interrupt sources. Using a greater number without IRQ sharing requires reading platform-specific registers. On such platforms, reading the IntCtl register to determine which interrupt corresponds to a timer interrupt will not work. On MIPSR2 systems there is a solution - the TI bit in the Cause register, specifically indicates that a timer interrupt has occured. This patch uses that bit to detect interrupts for MIPSR2 processors, which may be expected to work regardless of how the timer interrupt may be routed in the hardware. Signed-off-by: David VomLehn (dvomlehn@cisco.com) To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/804/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Add hugetlbfs page defines.David Daney1-0/+16
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-05-14MIPS: Fix sign-extension bug in 32-bit kernel on 32-bit hardware.Ralf Baechle1-4/+4
Probably nobody does arithmetic on cp0 register values so this has never bitten. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-05-14MIPS: Cavium: Add support for 8k and 32k page sizes.Ralf Baechle1-0/+11
Beyond the requirements of the architecture standard Cavium also supports 8k and 32k pages. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: David Daney <ddaney@caviumnetworks.com>
2009-05-14MIPS: SMTC: Bring set/clear/change_c0_## return value semantics uptodate.Kevin D. Kissell1-8/+11
Signed-off-by: Kevin D. Kissell <kevink@paralogos.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-23MIPS: Change {set,clear,change}_c0_<foo> to return old value.Ralf Baechle1-11/+11
This is more standard and useful and need for the following fix to work correctly. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Override assembler target architecture for octeon.David Daney1-0/+2
Gas from binutils 2.19 fails to compile some cop1 instructions with -march=octeon. Since the cop1 instructions are present in mips1, use that arch instead. This will be fixed in binutils 2.20. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add Cavium OCTEON specific register definitions to mipsregs.hDavid Daney1-0/+20
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-27MIPS: Add CONFIG_CPU_R5500 for NEC VR5500 series processorsShinya Kuribayashi1-0/+1
We already have sufficient infrastructure to support VR5500 and VR5500A series processors. Here's a Makefile support to make it selectable by ports, and enable it for NEC EMMA2RH Markeins board. This patch also fixes a confused target help, and adds 1Gb PageMask bits supported by VR5500 and its variants. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-11MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle1-0/+1526
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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