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2011-03-15m68knommu: limit interrupts supported by ColdFire intc-2 driverGreg Ungerer1-33/+25
The intc-2 interrupt controller on some ColdFire CPUs has a set range of interrupts its supports (64 through 128 or 192 depending on model). We shouldn't be setting this handler for every possible interrupt from 0 to 255. Set more appropriate limits, and this means we can drop the interrupt number check in the mask and unmask routines. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: add basic support for the ColdFire based FireBee boardGreg Ungerer3-0/+93
The FireBee is a ColdFire 5475 based board. Add a configuration option to support it, and the basic platform flash layout code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: make ColdFire internal peripheral region configurableGreg Ungerer1-0/+40
Most ColdFire CPUs have an internal peripheral set that can be mapped at a user selectable address. Different ColdFire parts either use an MBAR register of an IPSBAR register to map the peripheral region. Most boards use the Freescale default mappings - but not all. Make the setting of the MBAR or IPSBAR register configurable. And only make the selection available on the appropriate ColdFire CPU types. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: clean up use of MBAR for DRAM registers on ColdFire startGreg Ungerer1-3/+3
In some of the RAM size autodetection code on ColdFire CPU startup we reference DRAM registers relative to the MBAR register. Not all of the supported ColdFire CPUs have an MBAR, and currently this works because we fake an MBAR address on those registers. In an effort to clean this up, and eventually remove the fake MBAR setting make the DRAM register address definitions actually contain the MBAR (or IPSBAR as appropriate) value as required. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: remove use of MBAR in old-style ColdFire timerGreg Ungerer1-2/+2
Not all ColdFire CPUs that use the old style timer hardware module use an MBAR set peripheral region. Move the TIMER base address defines to the per-CPU header files where we can set it correctly based on how the peripherals are mapped - instead of using a fake MBAR for some platforms. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: move ColdFire DMA register addresses to per-cpu headersGreg Ungerer1-4/+4
The base addresses of the ColdFire DMA unit registers belong with all the other address definitions in the per-cpu headers. The current definitions assume they are relative to an MBAR register. Not all ColdFire CPUs have an MBAR register. A clean address define can only be acheived in the per-cpu headers along with all the other chips peripheral base addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: remove use of MBAR value for ColdFire 528x peripheral addressingGreg Ungerer1-7/+7
The ColdFire 528x family of CPUs does not have an MBAR register, so don't define its peripheral addresses relative to one. Its internal peripherals are relative to the IPSBAR register, so make sure to use that. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: remove use of MBAR value for ColdFire 527x peripheral addressingGreg Ungerer1-7/+7
The ColdFire 527x family of CPUs does not have an MBAR register, so don't define its peripheral addresses relative to one. Its internal peripherals are relative to the IPSBAR register, so make sure to use that. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: remove use of MBAR value for ColdFire 523x peripheral addressingGreg Ungerer1-5/+5
The ColdFire 523x family of CPUs does not have an MBAR register, so don't define its peripheral addresses relative to one. Its internal peripherals are relative to the IPSBAR register, so make sure to use that. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: remove MBAR and IPSBAR hacks for the ColdFire 520x CPUsGreg Ungerer2-20/+20
The ColdFire 5207 and 5208 CPUs have fixed peripheral addresses. They do not use the setable peripheral address registers like the MBAR and IPSBAR used on many other ColdFire parts. Don't use fake values of MBAR and IPSBAR when using peripheral addresses for them, there is no need to. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: move ColdFire PIT timer base addressesGreg Ungerer1-1/+1
The PIT hardware timer module used in some ColdFire CPU's is not always addressed relative to an IPSBAR register. Parts like the ColdFire 5207 and 5208 have fixed peripheral addresses. So lets not define the register addresses of the PIT relative to an IPSBAR definition. Move the base address definitions into the per-part headers. This is a lot more consistent since all the other peripheral base addresses are defined in the per-part header files already. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: remove kludge seting of MCF_IPSBAR for ColdFire 54xxGreg Ungerer1-8/+6
The ColdFire 54xx family shares the same interrupt controller used on the 523x, 527x and 528x ColdFire parts, but it isn't offset relative to the IPSBAR register. The 54xx doesn't have an IPSBAR register. By including the base address of the peripheral registers in the register definitions (MCFICM_INTC0 and MCFICM_INTC1 in this case) we can avoid having to define a fake IPSBAR for the 54xx. And this makes the register address definitions of these more consistent, the majority of the other register address defines include the peripheral base address already. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: Select GENERIC_HARDIRQS_NO_DEPRECATEDThomas Gleixner1-0/+1
All chips converted and proper accessor functions used. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: Use proper irq_desc accessors inThomas Gleixner1-2/+4
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: Convert 5249 intc irq_chip to new functionsThomas Gleixner1-10/+10
/me idly wonders what sets the handlers for this chip. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: Convert 5272 intc irq_chip to new functionsThomas Gleixner1-10/+18
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: Convert 68360 ints irq_chip to new functionsThomas Gleixner1-9/+9
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: Convert 68328 ints irq_chip to new functionsThomas Gleixner1-6/+6
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: Convert coldfire intc-simr irq_chip to newThomas Gleixner1-6/+12
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: Convert coldfire intc-2 irq_chip to newThomas Gleixner1-6/+10
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: Convert coldfire intc irq_chip to newThomas Gleixner1-10/+10
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-15m68knommu: 5772: Replace private irq flow handlerThomas Gleixner1-4/+1
That handler lacks the minimal checks for action being zero etc. Keep the weird flow - ack before handling - intact and call into handle_simple_irq which does the right thing. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Greg Ungerer <gerg@uclinux.org> LKML-Reference: <20110202212552.413849952@linutronix.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-02-16m68knommu: set flow handler for secondary interrupt controller of 5249Greg Ungerer1-1/+3
The secondary interrupt controller of the ColdFire 5249 code is not setting the edge triggered flow handler. Set it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-02-16m68knommu: remove use of IRQ_FLG_LOCK from 68360 platform supportGreg Ungerer2-2/+2
The m68knommu arch does not define or use IRQ_FLG_LOCK in its irq subsystem. Remove obsolete use of it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-02-16m68knommu: add missing linker __modver sectionGreg Ungerer1-0/+6
Add missing linker section __modver to fix: LD vmlinux /usr/local/bin/../m68k-uclinux/bin/ld.real: error: no memory region specified for loadable section `__modver' Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-02-16m68knommu: fix mis-named variable int set_irq_chip loopGreg Ungerer1-2/+2
Compiling for 68360 targets gives: CC arch/m68knommu/platform/68360/ints.o arch/m68knommu/platform/68360/ints.c: In function ‘init_IRQ’: arch/m68knommu/platform/68360/ints.c:135:16: error: ‘irq’ undeclared (first use in this function) arch/m68knommu/platform/68360/ints.c:135:16: note: each undeclared identifier is reported only once for each function it appears in Fix variable name used. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-02-16m68knommu: add optimize memmove() functionGreg Ungerer2-1/+106
Add an m68k/coldfire optimized memmove() function for the m68knommu arch. This is the same function as used by m68k. Simple speed tests show this is faster once buffers are larger than 4 bytes, and significantly faster on much larger buffers (4 times faster above about 100 bytes). This also goes part of the way to fixing a regression caused by commit ea61bc461d09e8d331a307916530aaae808c72a2 ("m68k/m68knommu: merge MMU and non-MMU string.h"), which breaks non-coldfire non-mmu builds (which is the 68x328 and 68360 families). They currently have no memmove() fucntion defined, since there was none in the m68knommu/lib functions. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-02-08m68knommu: fix use of un-defined _TIF_WORK_MASKGreg Ungerer3-3/+0
The _TIF_WORK_MASK definition was removed in the clean up of MMU and non-MMU arch/m68k/include/asm/thread_info*.h files (this was commit cddafa3500fde4a07e5bf899ec97a04069f8f7ce, "merge MMU and non-MMU thread_info.h"). It didn't get cleaned out of the entry.S code for the 68328 and 68360 based platforms. And it was replaced by a hard coded constant mask for coldfire platforms. There is currently no need to mask any of these bits, so fix all uses (and former uses) to check for any non-zero value. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-01-21m68knommu: Use generic irq KconfigThomas Gleixner1-4/+1
No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Greg Ungerer <gerg@uclinux.org>
2011-01-21genirq: Remove __do_IRQThomas Gleixner1-4/+0
All architectures are finally converted. Remove the cruft. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Richard Henderson <rth@twiddle.net> Cc: Mike Frysinger <vapier@gentoo.org> Cc: David Howells <dhowells@redhat.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Greg Ungerer <gerg@uclinux.org> Cc: Michal Simek <monstr@monstr.eu> Acked-by: David Howells <dhowells@redhat.com> Cc: Kyle McMartin <kyle@mcmartin.ca> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Chen Liqin <liqin.chen@sunplusct.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Chris Metcalf <cmetcalf@tilera.com> Cc: Jeff Dike <jdike@addtoit.com>
2011-01-20kconfig: rename CONFIG_EMBEDDED to CONFIG_EXPERTDavid Rientjes7-7/+7
The meaning of CONFIG_EMBEDDED has long since been obsoleted; the option is used to configure any non-standard kernel with a much larger scope than only small devices. This patch renames the option to CONFIG_EXPERT in init/Kconfig and fixes references to the option throughout the kernel. A new CONFIG_EMBEDDED option is added that automatically selects CONFIG_EXPERT when enabled and can be used in the future to isolate options that should only be considered for embedded systems (RISC architectures, SLOB, etc). Calling the option "EXPERT" more accurately represents its intention: only expert users who understand the impact of the configuration changes they are making should enable it. Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: David Woodhouse <david.woodhouse@intel.com> Signed-off-by: David Rientjes <rientjes@google.com> Cc: Greg KH <gregkh@suse.de> Cc: "David S. Miller" <davem@davemloft.net> Cc: Jens Axboe <axboe@kernel.dk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Robin Holt <holt@sgi.com> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-01-18Merge branch 'for-linus' of ↵Linus Torvalds14-243/+212
git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (25 commits) m68knommu: fix broken setting of irq_chip and handler m68knommu: switch to using -mcpu= flags for ColdFire targets m68knommu: arch/m68knommu/Kconfig whitespace cleanup m68knommu: create optimal separate instruction and data cache for ColdFire m68knommu: support ColdFire caches that do copyback and write-through m68knommu: support version 2 ColdFire split cache m68knommu: make cache push code ColdFire generic m68knommu: clean up ColdFire cache control code m68knommu: move inclusion of ColdFire v4 cache registers m68knommu: merge bit definitions for version 3 ColdFire cache controller m68knommu: create bit definitions for the version 2 ColdFire cache controller m68knommu: remove empty __iounmap() it is no used m68knommu: remove kernel_map() code, it is not used m68knommu: remove do_page_fault(), it is not used m68knommu: use user stack pointer hardware on some ColdFire cores m68knommu: remove command line printing DEBUG m68knommu: remove fasthandler interrupt code m68knommu: move UART addressing to part specific includes m68knommu: fix clock rate value reported for ColdFire 54xx parts m68knommu: move ColdFire CPU names into their headers ...
2011-01-07m68knommu: Need to check __get_user()/__put_user() resultAl Viro1-6/+6
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2011-01-07m68knommu: signal.c __user annotationsAl Viro1-28/+28
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2011-01-07m68knommu: Equivalent of "m68k: handle new gcc's"Al Viro1-14/+14
... from back in 2004; again, it's ifdefed out by CONFIG_FPU. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2011-01-07m68knommu: f_pcr has been gone since headers' mergeAl Viro1-4/+4
sure, it's effectively ifdefed out, but still... Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2011-01-07m68knommu: Don't lose state if sigframe setup failsAl Viro1-7/+12
exact parallel to m68k analog Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2011-01-07m68knommu: Handle multiple pending signalsAl Viro4-9/+8
we shouldn't bugger off to userland when there still are pending signals; among other things it makes e.g. SIGSEGV triggered by failure to build a sigframe to be delivered _now_ and not when we hit the next syscall or interrupt. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2011-01-07m68knommu: Switch to saner sigsuspendAl Viro5-66/+22
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2011-01-07m68knommu: Don't bother with SA_ONESHOTAl Viro1-3/+0
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2011-01-07m68knommu: fix broken setting of irq_chip and handlerGreg Ungerer1-2/+2
Fix compile error, by using correct loop variable: arch/m68knommu/platform/68328/ints.c: In function ‘init_IRQ’: arch/m68knommu/platform/68328/ints.c:182: error: ‘irq’ undeclared (first use in this function) arch/m68knommu/platform/68328/ints.c:182: error: (Each undeclared identifier is reported only once arch/m68knommu/platform/68328/ints.c:182: error: for each function it appears in.) Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-01-05m68knommu: switch to using -mcpu= flags for ColdFire targetsGreg Ungerer1-5/+5
Gcc has deprecated the use of the following ColdFire cpu options: -m5206e, -m528x, -m5307 and -m5407. In there place we should use the equivilent -mcpu= option and setting. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-01-05m68knommu: arch/m68knommu/Kconfig whitespace cleanupPhilippe De Muyter1-10/+10
Replace 8 spaces, or even 7, by TAB at begin of lines. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-01-05m68knommu: support ColdFire caches that do copyback and write-throughGreg Ungerer1-0/+24
The version 3 and version 4 ColdFire cache controllers support both write-through and copy-back modes on the data cache. Allow for Kconfig time configuration of this, and set the cache mode appropriately. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-01-05m68knommu: support version 2 ColdFire split cacheGreg Ungerer1-0/+32
The newer version 2 ColdFire CPU cores support a configurable cache arrangement. The cache memory can be used as all instruction cache, all data cache, or split in half for both instruction and data caching. Support this setup via a Kconfig time menu that allows a kernel builder to choose the arrangement they want to use. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-01-05m68knommu: make cache push code ColdFire genericGreg Ungerer2-1/+49
Currently the code to push cache lines is only available to version 4 cores. Version 3 cores may also need to use this if we support copy- back caches on them. Move this code to make it more generic, and useful for all version ColdFire cores. With this in place we can now have a single cache_flush_all() code path that does all the right things on all version cores. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-01-05m68knommu: clean up ColdFire cache control codeGreg Ungerer1-5/+21
The cache control code for the ColdFire CPU's is a big ugly mess of "#ifdef"ery liberally coated with bit constants. Clean it up. The cache controllers in the various ColdFire parts are actually quite similar. Just differing in some bit flags and options supported. Using the header defines now in place it is pretty easy to factor out the small differences and use common setup and flush/invalidate code. I have preserved the cache setups as they where in the old code (except where obviously wrong - like in the case of the 5249). Following from this it should be easy now to extend the possible setups used on the CACHE controllers that support split cacheing or copy-back or write through options. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-01-05m68knommu: remove empty __iounmap() it is no usedGreg Ungerer1-9/+0
The empty __iounmap() function is not used on m68knommu at all. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-01-05m68knommu: remove kernel_map() code, it is not usedGreg Ungerer2-34/+1
The kernel_map() functions is not used anywhere, remove it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-01-05m68knommu: remove do_page_fault(), it is not usedGreg Ungerer2-58/+1
The non-MMU m68k does not use the do_page_fault() code, so remove it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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