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2019-11-12csky: use generic ioremapChristoph Hellwig1-5/+3
Use the generic ioremap_prot and iounmap helpers. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Guo Ren <guoren@kernel.org>
2019-11-11csky: remove ioremap_cacheChristoph Hellwig1-2/+0
No driver that can be used on csky uses ioremap_cache, and this interface has been deprecated in favor of memremap. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Guo Ren <guoren@kernel.org>
2019-11-11arch: rely on asm-generic/io.h for default ioremap_* definitionsChristoph Hellwig1-1/+0
Various architectures that use asm-generic/io.h still defined their own default versions of ioremap_nocache, ioremap_wt and ioremap_wc that point back to plain ioremap directly or indirectly. Remove these definitions and rely on asm-generic/io.h instead. For this to work the backup ioremap_* defintions needs to be changed to purely cpp macros instea of inlines to cover for architectures like openrisc that only define ioremap after including <asm-generic/io.h>. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Palmer Dabbelt <palmer@dabbelt.com>
2019-08-15csky: Fixup ioremap function losingGuo Ren1-11/+12
Implement the following apis to meet usage in different scenarios. - ioremap (NonCache + StrongOrder) - ioremap_nocache (NonCache + StrongOrder) - ioremap_wc (NonCache + WeakOrder ) - ioremap_cache ( Cache + WeakOrder ) Also change flag VM_ALLOC to VM_IOREMAP in get_vm_area_caller. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Christoph Hellwig <hch@infradead.org>
2019-01-08csky: fixup CACHEV1 store instruction fast retireGuo Ren1-0/+25
For I/O access, 810/807 store instruction fast retire will cause wrong primitive. For example: stw (clear interrupt source) stw (unmask interrupt controller) enable interrupt stw is fast retire instruction. When PC is run at enable interrupt stage, the clear interrupt source hasn't finished. It will cause another wrong irq-enter. So use mb() to prevent above. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Lu Baoquan <lu.baoquan@intellif.com>
2018-10-25csky: Cache and TLB routinesGuo Ren1-0/+24
This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>