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2010-10-18Merge branches 'at91', 'dcache', 'ftrace', 'hwbpt', 'misc', 'mmci', 's3c', ↵Russell King154-945/+5693
'st-ux' and 'unwind' into devel
2010-10-18ARM: 6441/1: ux500: The platform is not just based on early drop silicon ↵Srinidhi Kasagar1-3/+1
version. Update Kconfig text accordingly. Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-11ARM: 6367/1: PL330: Accept different revisionJassi Brar1-4/+3
The driver can handle different revisions of the core which vary only minorly. Signed-off-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-08ARM: 6369/1: Update RealView SMP defconfigLinus Walleij1-2/+13
This patches the condensed RealView SMP defconfig activating the same 2.6.36 features mentioned in the vanilla RealView defconfig patch submitted earlier. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-08ARM: 6365/1: Update RealView defconfigLinus Walleij1-2/+13
This patches the condensed RealView defconfig activating some stuff that has been missing from this config for some time and some stuff that was merged in the 2.6.36 merge window: - The new character LCD driver is enabled - The Versatile I2C is enabled - The PL022 SPI driver is enabled - gpiolib is enabled (and makes MMC detection work properly) - The new LEDs code is enabled with a heartbeat trigger - The RTC class is enabled, and the PL031 RTC (onchip) and the offchip DS1307 on I2C is enabled Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-08ARM: vmlinux.lds: Move unwind tables into _stext.._etextRussell King1-2/+2
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-08ARM: vmlinux.lds: Refer to start of .data using _sdata rather than _dataRussell King3-4/+4
Use _sdata as the start of the data section, rather than _data. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-08ARM: 6428/1: add cpu_idle_wait() to support CPUidle on SMP systems.Kevin Hilman3-0/+24
In order for CPUidle to work on SMP systems, an implementation of cpu_idle_wait() is needed. This patch duplicates the x86 implementation of cpu_idle_wait() for ARM. Tested-by: Colin Cross <ccross@android.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-08ARM: 6429/1: Check for is_smp for tlb_ops and cache_ops broadcastTony Lindgren1-11/+17
Broadcast should not be needed when running SMP kernel on UP systems. Also, this fixes an undefined instruction for SMP_ON_UP on earlier ARM cores without the extended CPUID_EXT_MMFR3 register. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-08ARM: 6431/1: fix isb regression on CPU < v7Linus Walleij1-4/+5
The kernel does not compile for my ARM926EJ-S system U300 due to the isb instruction inserted in generic assember statement from commit 8925ec4c530094b878e7e28a1fd78e7122afd973, "ARM: 6385/1: setup: detect aliasing I-cache when D-cache is non-aliasing" hey the isb is only available when assembling for v7 so let's use the generic isb() macro from setup.h instead. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6386/1: flush_ptrace_access: invalidate correct I-cache aliasWill Deacon1-3/+20
copy_to_user_page can be used by access_process_vm to write to an executable page of a process using a mapping acquired by kmap. For systems with I-cache aliasing, flushing the I-cache using the Kernel mapping may leave stale data in the I-cache if the user mapping is of a different colour. This patch introduces a flush_icache_alias function to flush.c, which calls flush_icache_range with a mapping of the specified colour. flush_ptrace_access is then modified to call this new function instead of coherent_kern_range in the case of an aliasing I-cache and a non-aliasing D-cache. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6385/1: setup: detect aliasing I-cache when D-cache is non-aliasingWill Deacon2-5/+42
Currently, the Kernel assumes that if a CPU has a non-aliasing D-cache then the I-cache is also non-aliasing. This may not be true on ARM cores from v6 onwards, which may have aliasing I-caches but non-aliasing D-caches. This patch adds a cpu_has_aliasing_icache function, which is called from cacheid_init and adds CACHEID_VIPT_I_ALIASING to the cacheid when appropriate. A utility macro, icache_is_vipt_aliasing(), is also provided. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6366/1: Update U300 defconfigLinus Walleij1-35/+2
This mainly removes a lot of unused subsystems (as for the mainline drivers) in the U300 defconfig, switch of MMC debugging by default and enables debugfs on the builds. Once we merge the drivers we'll configure it on again. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6393/1: AT91: Add flexibity board supportMaxim Osipov3-0/+171
This patch adds support for Flexibity Connect platform from http://www.flexibity.com/ (AT91SAM9260 based). Signed-off-by: Maxim Osipov <maxim.osipov@gmail.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6405/1: Handle __flush_icache_all for CONFIG_SMP_ON_UPTony Lindgren4-27/+77
Do this by adding flush_icache_all to cache_fns for ARMv6 and 7. As flush_icache_all may neeed to be called from flush_kern_cache_all, add it as the first entry in the cache_fns. Note that now we can remove the ARM_ERRATA_411920 dependency to !SMP so it can be selected on UP ARMv6 processors, such as omap2. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6402/1: Don't send IPI in smp_send_stop if there's only one CPUTony Lindgren1-1/+2
No need to send IPI if there's one CPU, especially when booting systems with CONFIG_SMP_ON_UP that may not even support IPI. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: Allow SMP kernels to boot on UP systemsRussell King14-102/+237
UP systems do not implement all the instructions that SMP systems have, so in order to boot a SMP kernel on a UP system, we need to rewrite parts of the kernel. Do this using an 'alternatives' scheme, where the kernel code and data is modified prior to initialization to replace the SMP instructions, thereby rendering the problematical code ineffectual. We use the linker to generate a list of 32-bit word locations and their replacement values, and run through these replacements when we detect a UP system. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: Provide common header for hard_smp_processor_id()Russell King7-53/+18
Provide a common header to read the SMP CPU number from the MPIDR. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: Simplify SMP/SCU/TWD dependenciesRussell King1-10/+7
All platforms which currently support SMP also support the ARM SCU and ARM TWD blocks, so it's pointless to make these config symbols conditional on the platform symbols which SMP is already conditional on. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6349/1: sa1111: move __sa1111_probe() to .devinit.textUwe Kleine-König1-1/+1
__sa1111_probe is only called by sa1111_probe that lives in .devinit.text. So it's save to move the former to .devinit.text, too. Acked-by: Kristoffer Ericson <kristoffer.ericson@gmail.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6293/1: coresight: cosmetic fixesAlexander Shishkin1-11/+11
Use BIT() macro whenever it is sensible to do so. Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Alexander Shishkin <virtuoso@slind.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6291/1: coresight: move struct tracectx inside etm driverAlexander Shishkin2-12/+15
This is done so as to be able to make use of the coresight components' registers in assembler code (like omap sleep code). Also, there shouldn't be any users of this structure outside the etm driver. Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Alexander Shishkin <virtuoso@slind.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6418/1: ux500: rename DB8500 DMA event line macrosRabin Vincent2-143/+133
Change the DMA event line macros to have the name of the SoC. Also, have the event line number encoded in the macro since on DB5500 several event lines are present at multiple alternate numbers. Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6417/1: ux500: build configuration for DB5500 mbox and modem irq handlerLinus Walleij2-0/+16
This rounds of the DB5500 mailbox patches by adding the Kconfig options to enable the modem IRQs and mailboxes. Signed-off-by: Stefan Nilsson XK <stefan.xk.nilsson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6415/1: ux500: DB5500 mailbox driverLinus Walleij2-0/+655
This is a driver for the mailboxes used to communicate with the DB5500 modem portions. Signed-off-by: Stefan Nilsson XK <stefan.xk.nilsson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6414/1: ux500: DB5500 generic modem IRQ handlerLinus Walleij1-0/+139
This is a (threaded) IRQ handler for the modems that appear from the modem part of the DB5500 ASIC. Signed-off-by: Stefan Nilsson XK <stefan.xk.nilsson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-04ARM: 6413/1: ux500: resources for DB5500 mbox driver and modem irq handlerLinus Walleij4-1/+117
Platform resources found in the DB5500 for mailboxes and the modem IRQ controller. Signed-off-by: Stefan Nilsson XK <stefan.xk.nilsson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-27Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds24-74/+199
* master.kernel.org:/home/rmk/linux-2.6-arm: (28 commits) ARM: 6411/1: vexpress: set RAM latencies to 1 cycle for PL310 on ct-ca9x4 tile ARM: 6409/1: davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE ARM: 6408/1: omap: Map only available sram memory ARM: 6407/1: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries ARM: pxa: remove pr_<level> uses of KERN_<level> ARM: pxa168fb: clear enable bit when not active ARM: pxa: fix cpu_is_pxa*() not expanding to zero when not configured ARM: pxa168: fix corrected reset vector ARM: pxa: Use PIO for PI2C communication on Palm27x ARM: pxa: Fix Vpac270 gpio_power for MMC ARM: 6401/1: plug a race in the alignment trap handler ARM: 6406/1: at91sam9g45: fix i2c bus speed leds: leds-ns2: fix locking ARM: dove: fix __io() definition to use bus based offset dmaengine: fix interrupt clearing for mv_xor ARM: kirkwood: Unbreak PCIe I/O port ARM: Fix build error when using KCONFIG_CONFIG ARM: 6383/1: Implement phys_mem_access_prot() to avoid attributes aliasing ARM: 6400/1: at91: fix arch_gettimeoffset fallout ARM: 6398/1: add proc info for ARM11MPCore/Cortex-A9 from ARM ...
2010-09-27ARM: 6411/1: vexpress: set RAM latencies to 1 cycle for PL310 on ct-ca9x4 tileWill Deacon1-1/+7
The PL310 on the ct-ca9x4 tile for the Versatile Express does not need to add additional latency when accessing its cache RAMs. Unfortunately, the boot monitor sets this up for an 8-cycle delay on reads and writes, resulting in greatly reduced memory performance when the L2 cache is enabled. This patch sets the L2 RAM latencies to the correct value of 1 cycle on the ct-ca9x4 tile before enabling the L2 cache. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-25ARM: 6409/1: davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICESantosh Shilimkar4-8/+4
On Davinci SRAM is mapped as MT_DEVICE becasue of the section mapping pre-requisite instead of intended MT_MEMORY_NONCACHED Since the section mapping limitation gets fixed with first patch in this series, the MT_MEMORY_NONCACHED can be used now. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-25ARM: 6408/1: omap: Map only available sram memorySantosh Shilimkar1-20/+5
Currently we map 1 MB section while setting up SRAM on OMAPs Regardless of the actual memory. The physical OCM RAM available on OMAP SOCs is in order of KBs. This patch maps only available sram and cleans up some un-necessary cpu_is_xxx checks. Mapping un-available or non-accessible(secure) memory on the newer ARM processor is dangerous. Because ARM CPUs can now speculatively prefetch, we should avoid mapping any no-existing or secure memory. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-25ARM: 6407/1: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entriesSantosh Shilimkar1-2/+15
This patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED types so that at boot-up, we can map memories outside system memory at page level granularity Previously the mapping was limiting to section level, which creates unnecessary additional mapping for which physical memory may not present. On the newer ARM with speculation, this is dangerous and can result in untraceable aborts. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-25Merge branch 'fix' of ↵Russell King5-4/+25
git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
2010-09-25ARM: pxa: remove pr_<level> uses of KERN_<level>Joe Perches1-2/+1
Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-09-25ARM: pxa: fix cpu_is_pxa*() not expanding to zero when not configuredEric Miao1-0/+12
When CONFIG_PXA3xx is not selected, cpu_is_pxa3xx() doesn't expand to zero, which in some places doesn't result in correct optimization. Signed-off-by: Eric Miao <eric.y.miao@gmail.com> Reported-and-tested-by: Marek Vasut <marek.vasut@gmail.com>
2010-09-25ARM: pxa168: fix corrected reset vectorMark F. Brown1-1/+6
Reset vector for pxa168 is 0xffff_0000 not 0x0. This fix allows reboot to work Signed-off-by: Mark F. Brown <mark.brown314@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-09-25ARM: pxa: Use PIO for PI2C communication on Palm27xMarek Vasut1-1/+5
Original idea by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2010-09-25ARM: pxa: Fix Vpac270 gpio_power for MMCMarek Vasut1-0/+1
GPIO 0 is valid, yet this platform doesn't have any power GPIO for MMC. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2010-09-23ARM: 6401/1: plug a race in the alignment trap handlerNicolas Pitre1-2/+17
When the policy for user space is to ignore misaligned accesses from user space, the processor then performs a documented rotation on the accessed data. This is the result of the access being trapped, and the kernel disabling the alignment trap before returning to user space again. In kernel space we always want misaligned accesses to be fixed up. This is enforced by always re-enabling the alignment trap on every entry into kernel space from user space. No such re-enabling is performed when an exception occurs while already in kernel space as the alignment trap is always supposed to be enabled in that case. There is however a small race window when a misaligned access in user space is trapped and the alignment trap disabled, but the CPU didn't return to user space just yet. Any exception would be entered from kernel space at that point and the kernel would then execute with the alignment trap disabled. Thanks to Maxime Bizon <mbizon@freebox.fr> for providing a test module that made this issue reproducible. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-23ARM: 6406/1: at91sam9g45: fix i2c bus speedPeter Korsgaard1-2/+2
Use a correct udelay value to get bus speed around 100KHz. The udelay value was most likely copied from the older devices, but the 9g45 is signicantly faster (400MHz, DDR, ..), so a udelay of 2 gives a bus speed of around 190KHz, which is too fast for some devices. A udelay value of 5 gives a bus speed of around 90KHz here. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-23Merge branch 'for-rmk' of ↵Russell King3-6/+6
git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion
2010-09-22arm: fix "arm: fix pci_set_consistent_dma_mask for dmabounce devices"FUJITA Tomonori5-1/+21
This fixes the regression caused by the commit 6fee48cd330c68 ("dma-mapping: arm: use generic pci_set_dma_mask and pci_set_consistent_dma_mask"). ARM needs to clip the dma coherent mask for dmabounce devices. This restores the old trick. Note that strictly speaking, the DMA API doesn't allow architectures to do such but I'm not sure it's worth adding the new API to set the dma mask that allows architectures to clip it. Reported-by: Krzysztof Halasa <khc@pm.waw.pl> Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-09-19ARM: dove: fix __io() definition to use bus based offsetEric Miao1-3/+3
Signed-off-by: Eric Miao <eric.miao@canonical.com> Acked-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
2010-09-19ARM: kirkwood: Unbreak PCIe I/O portArnaud Patard2-3/+3
The support for the 2 pcie port of the 6282 has broken i/o port by switching *_IO_PHYS_BASE and *_IO_BUS_BASE. In fact, the patches reintroduced the same bug solved by commit 35f029e2514be209eb0e88c7d927f3bcc42a5cc2. So, I'm adding back *_IO_BUS_BASE in resource declaration and fix definition of KIRKWOOD_PCIE1_IO_BUS_BASE. With this change, the xgi card on my t5325 is working again. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Acked-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net> Cc: stable@kernel.org
2010-09-19Merge branch 's5p-fixes-for-linus' of ↵Linus Torvalds9-66/+107
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung * 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: S3C64XX: Add IORESOURCE_IRQ_HIGHLEVEL flag to dm9000 on mach-real6410 ARM: S3C64XX: Fix coding style errors on mach-real6410 ARM: S3C64XX: Prototype SPI devices ARM: S3C64XX: Fix dev-spi build ARM: SAMSUNG: Fix on s5p_gpio_[get,set]_drvstr ARM: SAMSUNG: Fix on drive strength value ARM: S5PV210: Add FIMC clocks ARM: S5PV210: Reduce the iodesc length of systimer ARM: S5PV210: Update I2C-1 Clock Register Property. ARM: S5P: Decrease IO Registers memory region size on FIMC ARM: S5P: Fix DMA coherent mask for FIMC
2010-09-19ARM: Fix build error when using KCONFIG_CONFIGRussell King1-1/+1
Jonathan Cameron reports that when using the environment variable KCONFIG_CONFIG, he encounters this error: make[2]: *** No rule to make target `.config', needed by `arch/arm/boot/compressed/vmlinux.lds' Reported-by: Jonathan Cameron <jic23@cam.ac.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-19ARM: 6383/1: Implement phys_mem_access_prot() to avoid attributes aliasingCatalin Marinas2-0/+18
ARMv7 onwards requires that there are no aliases to the same physical location using different memory types (i.e. Normal vs Strongly Ordered). Access to SO mappings when the unaligned accesses are handled in hardware is also Unpredictable (pgprot_noncached() mappings in user space). The /dev/mem driver requires uncached mappings with O_SYNC. The patch implements the phys_mem_access_prot() function which generates Strongly Ordered memory attributes if !pfn_valid() (independent of O_SYNC) and Normal Noncacheable (writecombine) if O_SYNC. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-19ARM: 6382/1: Remove superfluous flush_kernel_dcache_page()Catalin Marinas1-3/+0
Since page cache pages are now considered 'dirty' by default, the cache flushing is handled via __flush_dcache_page() when a page gets mapped to user space. Highmem pages on VIVT systems are flushed during kunmap() and flush_kernel_dcache_page() was already a no-op in this case. ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE is still defined since ARM needs specific implementations for flush_kernel_vmap_range() and invalidate_kernel_vmap_range(). Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-19ARM: 6381/1: Use lazy cache flushing on ARMv7 SMP systemsCatalin Marinas2-9/+8
ARMv7 processors like Cortex-A9 broadcast the cache maintenance operations in hardware. This patch allows the flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode similar to the UP case. Note that cache flushing on SMP systems now takes place via the set_pte_at() call (__sync_icache_dcache) and there is no race with other CPUs executing code from the new PTE before the cache flushing took place. Tested-by: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-19ARM: 6380/1: Introduce __sync_icache_dcache() for VIPT cachesCatalin Marinas4-6/+64
On SMP systems, there is a small chance of a PTE becoming visible to a different CPU before the current cache maintenance operations in update_mmu_cache(). To avoid this, cache maintenance must be handled in set_pte_at() (similar to IA-64 and PowerPC). This patch provides a unified VIPT cache handling mechanism and implements the __sync_icache_dcache() function for ARMv6 onwards architectures. It is called from set_pte_at() and replaces the update_mmu_cache(). The latter is still used on VIVT hardware where a vm_area_struct is required. Tested-by: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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