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2013-04-12Merge tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Olof Johansson77-749/+838
into next/soc2 From Shawn Guo: The imx soc changes for 3.10: * Enable anatop, well bisa and RBC for suspend to optimize the power consumption a little bit * Clock changes for TVE, LDB, PATA, SRTC support * Add System Reset Controller (SRC) support for imx5 and imx6 * Add initial imx6dl support based on imx6q code * Kconfig for cpufreq-cpu0, defconfig updates and few other changes * tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: (275 commits) ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock ARM i.MX53: tve_di clock is not part of the CCM, but of TVE ARM i.MX53: make tve_ext_sel propagate rate change to PLL ARM i.MX53: Remove unused tve_gate clkdev entry ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree ARM: i.MX5: Add PATA and SRTC clocks ARM: imx: do not bring up unavailable cores ARM: imx: add initial imx6dl support ARM: imx1: mm: add call to mxc_device_init ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS ARM: i.MX53 Add the cko1, cko2 clock outputs. staging: drm/imx: Use SRC to reset IPU ARM i.MX6q: Add GPU, VPU, IPU, and OpenVG resets to System Reset Controller (SRC) ARM: imx: do not use regmap_read for ANADIG_DIGPROG ARM i.MX6q: set the LDB serial clock parent to the video PLL ARM i.MX6q: Add audio/video PLL post dividers for i.MX6q rev 1.1 ARM i.MX6q: fix ldb di divider and selector clocks ARM i.MX53: fix ldb di divider and selector clocks ARM i.MX: Add imx_clk_divider_flags and imx_clk_mux_flags ... Signed-off-by: Olof Johansson <olof@lixom.net> Trivial change/change conflict in arch/arm/mach-imx/mach-imx6q.c resolved.
2013-04-12ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clockPhilipp Zabel1-2/+2
Use imx_clk_mux_flags to set the appropriate flags for the TVE selector clock. This is needed so tve_clk rate changes can propagate up to pll4_sw. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM i.MX53: tve_di clock is not part of the CCM, but of TVEPhilipp Zabel1-2/+1
Remove the tve_di clock from the CCM clock tree. It will be provided by the Television Encoder driver, as this clock is an output signal of the TVE module. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM i.MX53: make tve_ext_sel propagate rate change to PLLPhilipp Zabel1-2/+2
This is needed so the Television Encoder driver can set the rate on tve_clk and have it propagated up to pll4_sw. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM i.MX53: Remove unused tve_gate clkdev entryPhilipp Zabel1-1/+0
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM i.MX5: Remove tve_sel clock from i.MX53 clock treePhilipp Zabel1-2/+3
On i.MX53, there is only tve_ext_sel. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: i.MX5: Add PATA and SRTC clocksSascha Hauer1-0/+3
This adds the clock gates and the binding documentation for PATA and SRTC. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: imx: do not bring up unavailable coresShawn Guo1-2/+2
The i.MX6 Quad can be fused as i.MX6 Dual chip, and similarly i.MX6 DualLite can be fused as i.MX6 Solo. The actual number of available cores can be found out from SCU. Since we do not reflect the fusing thing in device tree, the function arm_dt_init_cpu_maps() will always call set_cpu_possible(true) for 4 cores on i.MX6 Quad/Dual and 2 cores for i.MX6 DualLite/Solo. This causes failures when kernel tries to bring those unavailable cores online. For example, the following failure message will be seen when booting an i.MX6 Solo chip. CPU1: failed to come online Though kernel will still boot fine, the message is somehow annoying. Let's get rid of it by calling set_cpu_possible(false) on those unavailable cores. While at it, the set_cpu_possible(true) for available cores is removed, since it's already been done in arm_dt_init_cpu_maps(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: imx: add initial imx6dl supportShawn Guo5-13/+36
The i.MX6 DualLite/Solo is another i.MX6 family SoC, which is highly compatible with i.MX6 Quad/Dual. And that's why we choose to support it using imx6q code with cpu_is_imx6dl() check when necessary. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: imx1: mm: add call to mxc_device_initGwenhael Goavec-Merou1-0/+2
mxc_device_init() is mandatory for mxc_aips and mxc_ahb bus registration, needed as parents, at least, for gpio and dma. Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFSFabio Estevam1-0/+1
Add CONFIG_GPIO_SYSFS as it is helpful for accessing GPIO from userspace. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTSFabio Estevam1-0/+1
Select CONFIG_PERF_EVENTS so that oprofile can be used. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: i.MX53 Add the cko1, cko2 clock outputs.Martin Fuzzey1-0/+34
These two clocks connect to external pins and can be muxed to various internal clocks. They are typically used either for debugging or to provide clocks to external chips (eg audio codecs). Currently only the selectable clocks that already exist in the clock tree have been added. Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM i.MX6q: Add GPU, VPU, IPU, and OpenVG resets to System Reset Controller ↵Philipp Zabel2-0/+66
(SRC) The SRC has auto-deasserting reset bits that control reset lines to the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset controller that can be controlled by those devices using the reset controller API. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: imx: do not use regmap_read for ANADIG_DIGPROGShawn Guo2-4/+13
Function imx_anatop_get_digprog() that reads register ANADIG_DIGPROG is called to identify silicon version. Users might query silicon version earlier than regmap subsystem is ready. For example, imx6q clock driver query revision in mx6q_clocks_init(), where regmap is not initialized yet. Change imx_anatop_get_digprog() to map anatop block and read ANADIG_DIGPROG in the native way, so that the function can work at very early stage. While at it, let's move imx_print_silicon_rev() back to imx6q_timer_init() to have the message show up a little earlier. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM i.MX6q: set the LDB serial clock parent to the video PLLPhilipp Zabel1-0/+5
On i.MX6q revision 1.1 and later, set the video PLL as parent for the LDB clock branch. On revision 1.0, the video PLL is useless due to missing dividers, so keep the default parent (mmdc_ch1_axi). Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM i.MX6q: Add audio/video PLL post dividers for i.MX6q rev 1.1Philipp Zabel1-6/+34
Query silicon revision to determine clock tree and add post dividers for newer revisions. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM i.MX6q: fix ldb di divider and selector clocksPhilipp Zabel1-4/+4
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate flags for the LDB display interface divider and selector clocks. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM i.MX53: fix ldb di divider and selector clocksPhilipp Zabel1-6/+6
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate flags for the LDB display interface divider and selector clocks. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM i.MX: Add imx_clk_divider_flags and imx_clk_mux_flagsPhilipp Zabel1-0/+17
The default is for dividers to set CLK_SET_PARENT_RATE and for muxes to not set that flag. In the LDB clock tree, we need the opposite, so add functions to create divider and mux clocks with configurable flags. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM i.MX6q: export imx6q_revisionPhilipp Zabel2-1/+2
So it can be used in clk-imx6q.c for revision dependent clock tree setup. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: imx27, imx5: Add kconfig selects for cpufreq-cpu0Markus Pargmann1-0/+3
There are some config options not selected by imx27 and imx5 that are necessary to use the cpufreq-cpu0 driver. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM i.MX53: Add GPU clocks to clock treePhilipp Zabel1-1/+8
This patch adds the missing GPU2D and GPU3D mux and gate clocks, and the graphics arbiter gate clock. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: mach-imx: anatop: Include "common.h"Fabio Estevam1-0/+1
Fix the following sparse warnings: arch/arm/mach-imx/anatop.c:56:6: warning: symbol 'imx_anatop_pre_suspend' was not declared. Should it be static? arch/arm/mach-imx/anatop.c:62:6: warning: symbol 'imx_anatop_post_resume' was not declared. Should it be static? arch/arm/mach-imx/anatop.c:68:6: warning: symbol 'imx_anatop_usb_chrg_detect_disable' was not declared. Should it be static? arch/arm/mach-imx/anatop.c:78:5: warning: symbol 'imx_anatop_get_digprog' was not declared. Should it be static? arch/arm/mach-imx/anatop.c:86:13: warning: symbol 'imx_anatop_init' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: imx: enable RBC to support anatop LPM modeAnson Huang4-1/+86
RBC is to control whether some ANATOP sub modules can enter lpm mode when SOC is into STOP mode, if RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP will have below behaviors: 1. Digital LDOs(CORE, SOC and PU) are bypassed; 2. Analog LDOs(1P1, 2P5, 3P0) are disabled; As the 2P5 is necessary for DRAM IO pre-drive in STOP mode, so we need to enable weak 2P5 in STOP mode when 2P5 LDO is disabled. For RBC settings, there are some rules as below due to hardware design: 1. All interrupts must be masked during operating RBC registers; 2. At least 2 CKIL(32K) cycles is needed after the RBC setting is changed. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: imx: enable periphery well bias for suspendAnson Huang1-1/+29
Enable periphery charge pump for well biasing at suspend to reduce periphery leakage. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: imx: enable anatop suspend/resumeAnson Huang6-44/+94
Anatop module have sereval configurations for user to reduce the power consumption in suspend, provide suspend/resume interface for further use and enable fet_odrive to reduce CORE LDO leakage during suspend. As we have a common anatop file, remove all the operations of anatop module in other files, use anatop interfaces to do that. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12Merge tag 'imx-cleanup-3.10' into imx/socShawn Guo18-533/+3
The imx cleanup for 3.10: * Clean up a couple of unneeded function declarations * Remove imx specific cpufreq driver as generic cpufreq-cpu0 works well as the replacement * Remove platform ahci support * Clean up unused ARCH/MACH Kconfig symbols * Remove a couple of unused files
2013-04-11Merge tag 'renesas-soc-r8a7790-for-v3.10' of ↵Olof Johansson2-1/+15
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2 From Simon Horman: Renesas ARM based r8a7790 SoC update for v3.10 * Force architecture timer to be activated regardless of bootloader - This is necessary for the lager board to boot * Add second memory range to r8a7790 PFC device - This is in preparation for further PFC work. It should not break anything as it is not used yet. This pull request is based on: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-soc2-for-v3.10 * tag 'renesas-soc-r8a7790-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: force enable of r8a7790 arch timer ARM: shmobile: Add second I/O range for r8a7790 PFC Signed-off-by: Olof Johansson <olof@lixom.net>
2013-04-09ARM: i.MX: remove unused ARCH_* configsPaul Bolle1-18/+0
This removes the unused Kconfig options ARCH_MX5, ARCH_MX51, ARCH_MX53 and MACH_MX21. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-09ARM i.MX53: remove platform ahci supportSascha Hauer4-172/+0
The i.MX53 ahci platform support is unused in mainline. To demotivate people using it just remove it from the tree. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-09Merge tag 'renesas-soc-r8a7778-for-v3.10' of ↵Arnd Bergmann3-16/+74
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2 From Simon Horman <horms+renesas@verge.net.au>: Renesas ARM r8a7778 SoC update for v3.10 Update to the r8a7778 SoC: * Add SH Ethernet support * Add r8a7778_init_irq_extpin() to allow configuration of IRQ0 - IRQ3 - This is a requirement for SMSC ethernet support * Cleanup: remove PLATFORM_INFO macro This pull request is based on: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10 * tag 'renesas-soc-r8a7778-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: R8A7778: add Ether support ARM: shmobile: r8a7778: add r8a7778_init_irq_extpin() ARM: shmobile: r8a7778: remove pointless PLATFORM_INFO() Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-09Merge tag 'renesas-soc-r8a7779-for-v3.10' of ↵Arnd Bergmann3-2/+46
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2 From Simon Horman <horms+renesas@verge.net.au>: Renesas ARM r8a7779 SoC update for v3.10 Update to the r8a7779 SoC: * Add SH Ethernet support * Add comment describing clock ratios This pull request is based on: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10 * tag 'renesas-soc-r8a7779-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: R8A7779: add Ether support ARM: shmobile: r8a7779: add each clocks ratio on comment area Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-09ARM: shmobile: force enable of r8a7790 arch timerMagnus Damm2-1/+14
Implement a SoC-specific timer init function for r8a7790 that makes sure the architected timer is started regardless of boot loader setting. Signed-off-by: Magnus Damm <damm@opensource.se> Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-09ARM i.MX6: Fix ldb_di clock selectionDirk Behme1-1/+1
According to the recent i.MX6 Quad technical reference manual, mode 0x4 (100b) of the CCM_CS2DCR register (address 0x020C402C) bits [11-9] and [14-12] select the PLL3 clock, and not the PLL3 PFD1 540M clock. In our code, the PLL3 root clock is named 'pll3_usb_otg', select this instead of the 540M clock. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-09ARM: imx: provide twd clock lookup from device treeShawn Guo2-1/+1
While booting from device tree, imx6q used to provide twd clock lookup by calling clk_register_clkdev() in clock driver. However, the commit bd60345 (ARM: use device tree to get smp_twd clock) forces DT boot to look up the clock from device tree. It causes the failure below when twd driver tries to get the clock, and hence kernel has to calibrate the local timer frequency. smp_twd: clock not found -2 ... Calibrating local timer... 396.13MHz. Fix the regression by providing twd clock lookup from device tree, and remove the unused twd clk_register_clkdev() call from clock driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-09ARM: imx35 Bugfix admux clockMarkus Pargmann1-0/+1
The admux clock seems to be the audmux clock as tests show. audmux does not work without this clock enabled. Currently imx35 does not register a clock device for audmux. This patch adds this registration. imx-audmux driver already handles a clock device, so no changes are necessary there. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Cc: stable@vger.kernel.org Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-09ARM: clk-imx35: Bugfix iomux clockMarkus Pargmann1-0/+1
This patch enables iomuxc_gate clock. It is necessary to be able to reconfigure iomux pads. Without this clock enabled, the clk_disable_unused function will disable this clock and the iomux pads are not configurable anymore. This happens at every boot. After a reboot (watchdog system reset) the clock is not enabled again, so all iomux pad reconfigurations in boot code are without effect. The iomux pads should be always configurable, so this patch always enables it. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Cc: stable@vger.kernel.org Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-09ARM: shmobile: Add second I/O range for r8a7790 PFCMagnus Damm1-0/+1
Add the GPIO I/O memory range to the r8a7790 PFC device. This extra I/O memory range is needed when using the PFC tables to drive both pin functions (using PINCTRL or function GPIO for old code) and actual GPIO. The goal is however to use a separate GPIO driver in the long run and when that happens this extra I/O memory range can be removed. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-08Merge branch 'gic/cleanup' into next/soc2Arnd Bergmann23-181/+10
Both zynq and shmobile have conflicts against the gic cleanup series, resolved here. Conflicts: arch/arm/mach-shmobile/smp-emev2.c arch/arm/mach-shmobile/smp-r8a7779.c arch/arm/mach-shmobile/smp-sh73a0.c arch/arm/mach-zynq/platsmp.c drivers/gpio/gpio-pl061.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-08Merge branch 'zynq/core-smp' of git://git.xilinx.com/linux-xlnx into next/soc2Arnd Bergmann20-438/+500
From Michal Simek <michal.simek@xilinx.com>: This branch is based on zynq/clksrc/cleanup parts because there are some dependencies on moving timer to generic location. I could based it on standard Linux tagged version but you will get several conflicts you will have to resolve. If you are OK to resolving these problems, please let me know I will create another branch with core-smp changes which are not based on zynq/clksrc/cleanup branch. * 'zynq/core-smp' of git://git.xilinx.com/linux-xlnx: arm: zynq: Add hotplug support arm: zynq: Add smp support arm: zynq: Add smp_twd timer arm: zynq: Get rid of xilinx function prefix arm: zynq: Add support for system reset arm: zynq: Move slcr initialization to separate file arm: zynq: Load scu baseaddress at run time Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-05ARM: shmobile: R8A7778: add Ether supportSergei Shtylyov3-0/+21
Add Ether clock and platform device for R8A7778 SoC; add a function to register this device with board-specific platform data. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-05ARM: shmobile: R8A7779: add Ether supportSergei Shtylyov3-2/+27
Add Ether clock and platform device for R8A7779 SoC; add a function to register this device with board-specific platform data. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-04ARM: shmobile: r8a7779: add each clocks ratio on comment areaKuninori Morimoto1-0/+19
Adding comment describing the r8a7779 clock frequencies depending on MD pin settings. Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-04arm: zynq: Add hotplug supportMichal Simek4-0/+113
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-04-04arm: zynq: Add smp supportMichal Simek7-0/+216
Zynq is dual core Cortex A9 which starts always at zero. Using simple trampoline ensure long jump to secondary_startup code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
2013-04-04arm: zynq: Add smp_twd timerMichal Simek1-0/+7
The zynq has a Cortex-A9 with the corresponding smp_twd timers. Use them. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-04-04arm: zynq: Get rid of xilinx function prefixMichal Simek1-11/+11
Xilinx is vendor name not SoC name. Use zynq instead. Also remove one checkpatch warning: WARNING: static const char * array should probably be static const char * const +static const char *xilinx_dt_match[] = { Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-04-04arm: zynq: Add support for system resetMichal Simek3-0/+34
Do system reset via slcr registers. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-04-04arm: zynq: Move slcr initialization to separate fileMichal Simek4-10/+74
Create separate slcr driver instead of polluting common code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-30 15:14:30 +0000