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2014-11-28Merge tag 'mvebu-soc-3.19' of git://git.infradead.org/linux-mvebu into next/socArnd Bergmann12-275/+166
Pull "mvebu SoC changes for v3.19" from Jason Cooper: - Armada 38x - Implement CPU hotplug support - Armada 375 - Remove Z1 stepping support (limited dist. of SoC) * tag 'mvebu-soc-3.19' of git://git.infradead.org/linux-mvebu: ARM: mvebu: Implement the CPU hotplug support for the Armada 38x SoCs ARM: mvebu: Fix the secondary startup for Cortex A9 SoC ARM: mvebu: Move SCU power up in a function ARM: mvebu: Clean-up the Armada XP support ARM: mvebu: update comments in coherency.c ARM: mvebu: remove Armada 375 Z1 workaround for I/O coherency ARM: mvebu: remove unused register offset definition ARM: mvebu: disable I/O coherency on non-SMP situations on Armada 370/375/38x/XP ARM: mvebu: make the coherency_ll.S functions work with no coherency fabric ARM: mvebu: Remove thermal quirk for A375 Z1 revision ARM: mvebu: add missing of_node_put() call in coherency.c ARM: orion: Fix for certain sequence of request_irq can cause irq storm ARM: mvebu: armada xp: Generalize use of i2c quirk Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-28ARM: add lolevel debug support for asm9260Oleksij Rempel2-2/+55
Since there is no public documentation, this patch also provide register offsets for different UART units on this SoC. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-28ARM: add mach-asm9260Oleksij Rempel2-0/+8
it is low cost (?) SoC targeted for market in China and India which trying to compete with AT91SAM9G25. Here is some info: http://www.alphascale.com/index.asp?ics/615.html One of products: http://www.aliexpress.com/store/product/2014-hot-sales-FREE-SHIPPING-new-Purple-core-ARM9-development-board-ASM9260T-SDRAM-power-line/433637_1931495721.html In some cases this SoC looks similar to iMX23/iMX28. But currently it makes no sense to merge mach code of this devices. Especially because most differences are already collected mach-mxs folder. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-28Merge tag 'imx-soc-3.19' of ↵Arnd Bergmann18-66/+438
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc Pull "The i.MX SoC update for 3.19" from Shawn Guo - Update i.MX6 suspend code to check DDR instead of CPU type, as the difference we need to handle is between LPDDR2 and DDR3, not SoCs. - Set anatop properly for LPDDR2 in DSM mode - Add support for new SoC LS1021A which integrates dual Cortex-A7 - Add ENET initialization for i.MX6SX platform - Add cpufreq support for i.MX53 platform - Add a SNVS based poweroff driver for i.MX6 platforms - Use ARM Global Timer as clocksource on VF610 Note: the change set is built on top of tag imx-fixes-3.18-2 to resolve a conflict on file arch/arm/mach-imx/clk-vf610.c. * tag 'imx-soc-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: power: reset: imx-snvs-poweroff: add power off driver for i.mx6 ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A ARM: imx: clk-vf610: get input clocks from assigned clocks ARM: imx: Add Freescale LS1021A SMP support ARM: imx: Add initial support for Freescale LS1021A ARM: imx53: add cpufreq support ARM: imx53: clk: add ARM clock ARM: imx: add CPU clock type ARM: imx5: add step clock, used when reprogramming PLL1 ARM: imx: add enet init for i.mx6sx ARM: imx6sx: add imx6sx iomux-gpr field define ARM: vf610: Add ARM Global Timer clocksource option ARM: imx: add anatop settings for LPDDR2 when enter DSM mode ARM: imx: replace cpu type check with ddr type check ARM: imx: Fix the removal of CONFIG_SPI option ARM: imx: clk-vf610: define PLL's clock tree Signed-off-by; Arnd Bergmann <arnd@arndb.de>
2014-11-28Merge (part of) tag 'omap-for-v3.19/hwmod-and-defconfig' of ↵Arnd Bergmann9-18/+208
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc SoC related changes for omaps including hwmod clean-up for DSS, and hwmod data for more UARTs and ADC. Also few defconfig changes to enable devices found on am335x and am437x. [arnd: I removed the defconfig changes from the branch in order to cherry-pick them onto the next/defconfig branch, but I did not change the other commits] * commit '29c4ce17bcad': ARM: dts: cm-t3x30: add keypad support ARM: OMAP2+: hwmod: AM43x: add hwmod support for ADC on AM43xx ARM: DRA7: hwmod data: Add missing UART hwmod data ARM: dts: omap4.dtsi: remove dss_fck ARM: OMAP4: fix RFBI iclk ARM: OMAP4: hwmod: use MODULEMODE properly ARM: OMAP4: hwmod: set DSS submodule parent hwmods ARM: OMAP5: hwmod: set DSS submodule parent hwmods ARM: OMAP2+: hwmod: add parent_hwmod support Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-28Merge tag 'samsung-pm-3' of ↵Arnd Bergmann4-25/+319
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc Pull "Samsung PM 3rd updates for v3.19" from Kukjin Kim: - exynos3250 : add PMU support - PMU refactoring : move restart code into PMU driver : move restart code for exynos440 into clk driver - use u8 for val[] in struct exynos_pmu_conf Note that this branch is based on tags/samsung-exynos-v3.19 * tag 'samsung-pm-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf ARM: EXYNOS: move restart code into pmu driver clk: exynos5440: move restart code into clock driver ARM: EXYNOS: add exynos3250 PMU support Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-28Merge tag 'samsung-exynos-v3.19' of ↵Arnd Bergmann12-174/+1063
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc Pull "Samsung exynos updates in arch/arm/mach-exynos/ for v3.19" from Kukjin Kim: - add SOC_EXYNOS4415 config to be used in audio driver - add support platform driver for exynos PMU - move PMU specific definitions from common.h to exynos-pmu.h - for exynos5420, add support PMU and Suspend-to-RAM use MCPM call backs and call regulator core suspend prepare and finish functions NOTE: including v3.19-next/non-critical-fixes, v3.19-next/cleanup-samsung and v3.19-next/pm-samsung-2 branches * tag 'samsung-exynos-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Call regulator core suspend prepare and finish functions ARM: EXYNOS: Use MCPM call-backs to support S2R on exynos5420 ARM: EXYNOS: Add Suspend-to-RAM support for exynos5420 ARM: EXYNOS: Add PMU support for exynos5420 ARM: EXYNOS: Move PMU specific definitions from common.h ARM: EXYNOS: Add platform driver support for Exynos PMU ARM: EXYNOS: Add support for exynos4415 SoC ARM: EXYNOS: fix typo in static struct name "exynos5_list_diable_wfi_wfe" ARM: EXYNOS: Fix CPU idle clock down after CPU off ARM: EXYNOS: Remove unneeded __ref annotation for cpu_die function ARM: EXYNOS: Move code from hotplug.c to platsmp.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-27ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_confBartlomiej Zolnierkiewicz1-1/+1
Values stored in val[] are never bigger than a byte. text data bss dec hex filename 7716 3692 8 11416 2c98 arch/arm/mach-exynos/pmu.o.before 5436 1908 8 7352 1cb8 arch/arm/mach-exynos/pmu.o.after Cc: Pankaj Dubey <pankaj.dubey@samsung.com> Cc: Amit Daniel Kachhap <amit.daniel@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-23ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021AArnd Bergmann1-4/+0
The newly introduced LS1021A SoC selects CONFIG_SOC_FSL, which is originally symbol used for the PowerPC based platforms and guards lots of code that does not build on ARM. This breaks allmodconfig, so let's remove it for now, until either all those drivers are fixed or they use a dependency on IMX instead. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-23ARM: imx: clk-vf610: get input clocks from assigned clocksStefan Agner1-5/+16
With the clock assignment device tree changes, the clocks get initialized properly but the search for those clocks fails with errors: [ 0.000000] i.MX clk 4: register failed with -17 [ 0.000000] i.MX clk 5: register failed with -17 This is because the module can't find those clocks anymore, and tries to initialize fixed clocks with the same name. Get the clock modules input clocks from the assigned clocks by default by using of_clk_get_by_name(). If this function returns not a valid clock, fall back to the old behaviour and search the input clock from the device tree's /clocks/$name node. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-23ARM: imx: Add Freescale LS1021A SMP supportJingchang Lu4-1/+36
Freescale LS1021A SoCs deploy two cortex-A7 processors, this adds bring-up support for the secondary core. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-23ARM: imx: Add initial support for Freescale LS1021AJingchang Lu3-0/+37
The LS1021A SoC is a dual-core Cortex-A7 based processor, this adds the initial support for it. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-23ARM: imx53: add cpufreq supportLucas Stach1-0/+2
Instanciate device for the generic cpufreq-dt driver. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-23ARM: imx53: clk: add ARM clockLucas Stach1-0/+5
The ARM clock is a virtual clock feeding the ARM partition of the SoC. It controls multiple other clocks to ensure the right sequencing when cpufreq changes the CPU clock rate. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx: add CPU clock typeLucas Stach3-1/+112
This implements a virtual clock used to abstract away all the steps needed in order to change the ARM clock, so we don't have to push all this clock handling into the cpufreq driver. While it will be used for i.MX53 at first it is generic enough to be used on i.MX6 later on. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx5: add step clock, used when reprogramming PLL1Lucas Stach1-1/+8
This is the bypass clock used to feed the ARM partition while we reprogram PLL1 to another rate. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx: add enet init for i.mx6sxFugang Duan1-0/+51
Add enet init for i.mx6sx: - Add phy ar8031 fixup - Set enet clock source from internal PLL Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: vf610: Add ARM Global Timer clocksource optionStefan Agner1-1/+20
Add the ARM Global Timer as clocksource/scheduler clock option and use it as default scheduler clock. This leaves the PIT timer for other users e.g. the secondary Cortex-M4 core. Also, the Global Timer has double the precission (running at pheripheral clock compared to IPG clock) and a 64-bit incrementing counter register. We still keep the PIT timer as an secondary option in case the ARM Global Timer is not available. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx: add anatop settings for LPDDR2 when enter DSM modeAnson Huang1-2/+32
For LPDDR2 platform, no need to enable weak2P5 in DSM mode, it can be pulled down to save power(~0.65mW). And per design team's recommendation, we should disconnect VDDHIGH and SNVS in DSM mode on i.MX6SL. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx: replace cpu type check with ddr type checkAnson Huang5-14/+30
As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3, we used cpu type to decide how to do these settings in suspend before which is NOT flexible, take i.MX6SL for example, although it has LPDDR2 on EVK board, but users can also use DDR3 on other boards, so it is better to read the DDR type from MMDC then decide how to do related settings. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-22ARM: EXYNOS: move restart code into pmu driverPankaj Dubey3-7/+23
Let's register restart handler from PMU driver for restart functionality. So that we can remove restart hooks from machine specific file, and thus moving ahead when PMU moved to driver folder, this functionality can be reused for ARM64 based Exynos SoC's. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22clk: exynos5440: move restart code into clock driverPankaj Dubey1-18/+1
Let's register restart handler for Exynos5440 from it's clock driver for restart functionality. So that we can cleanup restart hooks from machine specific file. CC: Sylwester Nawrocki <s.nawrocki@samsung.com> CC: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: EXYNOS: add exynos3250 PMU supportBartlomiej Zolnierkiewicz2-0/+295
This patch prepares the PMU code for the future: - suspend/resume (S2R) support - cpuidle AFTR/W-AFTR modes support on Exynos3250. Cc: Vikas Sajjan <vikas.sajjan@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> [kgene.kim@samsung.com: fixed coding style] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: mvebu: Implement the CPU hotplug support for the Armada 38x SoCsGregory CLEMENT3-3/+53
This commit implements the CPU hotplug support for the Marvell Armada 38x platform. Similarly to what was done for the Armada XP, this commit: * Implements the ->cpu_die() function of SMP operations by calling armada_38x_do_cpu_suspend() to enter the deep idle state for CPUs going offline. * Implements a dummy ->cpu_kill() function, simply needed for the kernel to know we have CPU hotplug support. * The mvebu_cortex_a9_boot_secondary() function makes sure to wake up the CPU if waiting in deep idle state by sending an IPI before deasserting the CPUs from reset. This is because mvebu_cortex_a9_boot_secondary() is now used in two different situations: for the initial boot of secondary CPUs (where CPU reset deassert is used to wake up CPUs) and for CPU hotplug (where an IPI is used to take CPU out of deep idle). * At boot time, we exit from the idle state in the ->smp_secondary_init() hook. This commit has been tested using CPU hotplug through sysfs (/sys/devices/system/cpu/cpuX/online) and using kexec. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1414669184-16785-5-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: Fix the secondary startup for Cortex A9 SoCGregory CLEMENT1-0/+1
During the secondary startup the SCU was assumed to be in normal mode. It is not always the case, and especially after a kexec. This commit adds the needed sequence to put the SCU in normal mode. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1414669184-16785-4-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: Move SCU power up in a functionGregory CLEMENT1-7/+13
This will allow reusing the same function in the secondary_startup for the Cortex A9 SoC. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1414669184-16785-3-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: Clean-up the Armada XP supportGregory CLEMENT7-9/+8
This patch removes the unneeded include of the armada-370-xp.h header. It also moves some declarations from this file into more accurate places. Finally, it also adds a comment explaining that we can't remove yet the smp field in the dt machine struct due to backward compatibly of the device tree. In a few releases, when the old device tree will be obsolete, we will be able to remove the smp field and then the armada-370-xp.h header. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1414669184-16785-2-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: update comments in coherency.cThomas Petazzoni1-2/+3
The coherency.c top-level comment mentions that it supports the coherency fabric for Armada 370 and XP, but it also supports the coherency fabric on Armada 375 and 38x, so this commit updates the comment accordingly. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1415871540-20302-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: remove Armada 375 Z1 workaround for I/O coherencyThomas Petazzoni1-166/+3
This reverts commit 5ab5afd8ba83 ("ARM: mvebu: implement Armada 375 coherency workaround"), since we are removing the support for the very early Z1 revision of the Armada 375 SoC. This commit is an exact revert, with two exceptions: - minor adaptations needed due to other changes that have taken place in coherency.c since the original commit - keep the definition of pr_fmt. This shouldn't originally have been part of the Armada 375 Z1 workaround commit since it had nothing to do with it. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1415871540-20302-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: remove unused register offset definitionThomas Petazzoni1-2/+0
Since commit b21dcafea36d ("arm: mvebu: remove dependency of SMP init on static I/O mapping"), the COHERENCY_FABRIC_CFG_OFFSET register offset definition is no longer used, so this commit removes it. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1415871540-20302-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: disable I/O coherency on non-SMP situations on Armada 370/375/38x/XPThomas Petazzoni1-14/+30
Enabling the hardware I/O coherency on Armada 370, Armada 375, Armada 38x and Armada XP requires a certain number of conditions: - On Armada 370, the cache policy must be set to write-allocate. - On Armada 375, 38x and XP, the cache policy must be set to write-allocate, the pages must be mapped with the shareable attribute, and the SMP bit must be set Currently, on Armada XP, when CONFIG_SMP is enabled, those conditions are met. However, when Armada XP is used in a !CONFIG_SMP kernel, none of these conditions are met. With Armada 370, the situation is worse: since the processor is single core, regardless of whether CONFIG_SMP or !CONFIG_SMP is used, the cache policy will be set to write-back by the kernel and not write-allocate. Since solving this problem turns out to be quite complicated, and we don't want to let users with a mainline kernel known to have infrequent but existing data corruptions, this commit proposes to simply disable hardware I/O coherency in situations where it is known not to work. And basically, the is_smp() function of the kernel tells us whether it is OK to enable hardware I/O coherency or not, so this commit slightly refactors the coherency_type() function to return COHERENCY_FABRIC_TYPE_NONE when is_smp() is false, or the appropriate type of the coherency fabric in the other case. Thanks to this, the I/O coherency fabric will no longer be used at all in !CONFIG_SMP configurations. It will continue to be used in CONFIG_SMP configurations on Armada XP, Armada 375 and Armada 38x (which are multiple cores processors), but will no longer be used on Armada 370 (which is a single core processor). In the process, it simplifies the implementation of the coherency_type() function, and adds a missing call to of_node_put(). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Fixes: e60304f8cb7bb545e79fe62d9b9762460c254ec2 ("arm: mvebu: Add hardware I/O Coherency support") Cc: <stable@vger.kernel.org> # v3.8+ Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1415871540-20302-3-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: make the coherency_ll.S functions work with no coherency fabricThomas Petazzoni1-2/+19
The ll_add_cpu_to_smp_group(), ll_enable_coherency() and ll_disable_coherency() are used on Armada XP to control the coherency fabric. However, they make the assumption that the coherency fabric is always available, which is currently a correct assumption but will no longer be true with a followup commit that disables the usage of the coherency fabric when the conditions are not met to use it. Therefore, this commit modifies those functions so that they check the return value of ll_get_coherency_base(), and if the return value is 0, they simply return without configuring anything in the coherency fabric. The ll_get_coherency_base() function is also modified to properly return 0 when the function is called with the MMU disabled. In this case, it normally returns the physical address of the coherency fabric, but we now check if the virtual address is 0, and if that's case, return a physical address of 0 to indicate that the coherency fabric is not enabled. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.8+ Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1415871540-20302-2-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22Merge branch 'mvebu/fixes' into mvebu/socJason Cooper3-5/+35
2014-11-21ARM: dts: cm-t3x30: add keypad supportDmitry Lifshitz1-0/+17
Add twl4030 matrtix keypad support. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-11-21Merge tag 'for-v3.19/omap-b2' of ↵Tony Lindgren8-18/+191
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.19/soc Several more OMAP patches targeted for v3.19. They include: - OMAP4/5: DSS hwmod cleanup patches from Tomi Valkeinen. - DRA7xx: hwmod data support for UARTs 7 through 10. - AM43xx: hwmod data support for the onboard ADC. Basic build, boot, and PM test reports are here: http://www.pwsan.com/omap/testlogs/omap-b-for-v3.19/20141121110550/ Note that I cannot test the DRA7xx or AM43xx patches, since I do not have these boards.
2014-11-21Merge branch 'adc-support-v3.19' into omap-b-for-v3.19Paul Walmsley1-0/+39
2014-11-21ARM: OMAP2+: hwmod: AM43x: add hwmod support for ADC on AM43xxVignesh R1-0/+39
This patch adds hwmod support for ADC on AM43xx. Since clockdomain and offsets of adc_tsc are different from AM33xx, ADC data has been directly added to AM43xx hwmod file. Signed-off-by: Vignesh R <vigneshr@ti.com> [paul@pwsan.com: fixed spelling of "Anolog"; converted spaces to tabs] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-11-21ARM: EXYNOS: Call regulator core suspend prepare and finish functionsJavier Martinez Canillas1-0/+23
The regulator framework has a set of helpers functions to be used when the system is entering and leaving from suspend but these are not called on Exynos platforms. This means that the .set_suspend_* function handlers defined by regulator drivers are not called when the system is suspended. Suggested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-21ARM: EXYNOS: Use MCPM call-backs to support S2R on exynos5420Abhilash Kesavan3-15/+78
Use the MCPM layer to handle core suspend/resume on Exynos5420. Also, restore the entry address setup code post-resume. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-21ARM: EXYNOS: Add Suspend-to-RAM support for exynos5420Vikas Sajjan1-2/+149
Adds Suspend-to-RAM support for EXYNOS5420 Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-21ARM: EXYNOS: Add PMU support for exynos5420Abhilash Kesavan2-0/+514
Adds initial PMU settings for exynos5420. This is required for future S2R and Switching support. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-21ARM: EXYNOS: Move PMU specific definitions from common.hPankaj Dubey5-18/+45
This patch moves PMU specific definitions into a new file as exynos-pmu.h. This will help in reducing dependency of common.h in pmu.c. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-21ARM: EXYNOS: Add platform driver support for Exynos PMUPankaj Dubey2-42/+130
This patch modifies Exynos Power Management Unit (PMU) initialization implementation in following way: - Added platform driver support for Exynos PMU IP. - Added platform struct exynos_pmu_data to hold platform specific data. - For each SoC's PMU support now we can add platform data and statically bind PMU configuration and SoC specific initialization function. - Separate each SoC's PMU initialization function and make it as part of platform data. - It also removes uses of soc_is_exynosXYZ(). Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-21ARM: EXYNOS: Add support for exynos4415 SoCChanwoo Choi2-0/+7
This patch adds support for Exynos4415 SoC. Exynos4415 is based on the 32-bit RISC processor for Smartphone. Exynos4415 has Cortex A9 quad-cores and has a target speed of 1.6GHz and provides 8.5GB/s memory bandwidth. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-21Merge branch 'v3.19-next/non-critical-fixes' into v3.19-next/mach-exynosKukjin Kim1-4/+4
2014-11-21Merge branch 'v3.19-next/cleanup-samsung' into v3.19-next/mach-exynosKukjin Kim5-96/+116
2014-11-21Merge tag 'renesas-soc4-for-v3.19' of ↵Arnd Bergmann6-1/+135
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Pull "Fourth Round of Renesas ARM Based SoC Updates for v3.19" from Simon Horman: * Add early debugging support using SCIF(A) * tag 'renesas-soc4-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Add early debugging support using SCIF(A) Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-21Merge tag 'berlin-soc-3.19-2' of ↵Arnd Bergmann1-1/+0
git://git.infradead.org/users/hesselba/linux-berlin into next/soc Pull "Berlin SoC changes for v3.19 (round 2)" from Sebastian Hesselbarth: - Do not select RESET_CONTROLLER as it is user selectable * tag 'berlin-soc-3.19-2' of git://git.infradead.org/users/hesselba/linux-berlin: ARM: berlin: do not select RESET_CONTROLLER Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-21ARM: BCM5301X: fix early serial consoleHauke Mehrtens1-2/+2
This device actually has a 8250 serial with a shift of 0. Tested this on a BCM4708. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-20Merge tag 'sunxi-core-for-3.19' of ↵Arnd Bergmann4-1/+27
git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/soc Pull "Allwinner Core Additions for 3.19" from Maxime Ripard: This has mostly been about introducing A80 support * tag 'sunxi-core-for-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: ARM: sunxi: make sun6i SMP ops static ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER and RESET_CONTROLLER for sun9i Documentation: sunxi: Add A80 datasheet link devicetree: bindings: Document supported Allwinner sunxi SoCs ARM: sunxi: Introduce Allwinner A80 support devicetree: bindings: Add vendor prefix for Merrii Technology Co., Ltd. ARM: sunxi: Add debug uart used by sun9i (Allwinner A80) Documentation: sunxi: Update Allwinner SoC documentation (A31/A31s/A23) Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-04 21:55:31 +0000