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2013-09-12arch: mm: pass userspace fault flag to generic fault handlerJohannes Weiner1-7/+10
2013-09-12arch: mm: do not invoke OOM killer on kernel fault OOMJohannes Weiner1-7/+7
2013-09-11mm: migrate: check movability of hugepage in unmap_and_move_huge_page()Naoya Horiguchi1-0/+5
2013-09-10Merge tag 'devicetree-for-linus' of git://git.secretlab.ca/git/linuxLinus Torvalds1-2/+1
2013-09-03arm64: mm: permit use of tagged pointers at EL0Will Deacon1-1/+1
2013-09-02arm64: Remove unused cpu_name ascii in arch/arm64/mm/proc.SCatalin Marinas1-4/+0
2013-08-28arm64: Fix mapping of memory banks not ending on a PMD_SIZE boundaryCatalin Marinas1-2/+21
2013-07-24of: Specify initrd location using 64-bitSantosh Shilimkar1-2/+1
2013-07-19arm64: mm: don't treat user cache maintenance faults as writesWill Deacon1-26/+20
2013-07-10mm: remove free_area_cacheMichel Lespinasse1-2/+0
2013-07-03mm/microblaze: prepare for removing num_physpages and simplify mem_init()Jiang Liu1-1/+1
2013-07-03mm/ARM64: prepare for removing num_physpages and simplify mem_init()Jiang Liu1-45/+3
2013-07-03mm: concentrate modification of totalram_pages into the mm coreJiang Liu1-1/+1
2013-07-03mm/ARM64: kill poison_init_mem()Jiang Liu1-14/+3
2013-07-03mm: enhance free_reserved_area() to support poisoning memory with zeroJiang Liu1-2/+2
2013-07-03mm: change signature of free_reserved_area() to fix building warningsJiang Liu1-1/+1
2013-07-01Merge branch 'for-next/hugepages' of git://git.linaro.org/people/stevecapper/...Catalin Marinas4-21/+88
2013-06-14ARM64: mm: HugeTLB support.Steve Capper3-15/+75
2013-06-14ARM64: mm: Restore memblock limit when map_mem finished.Steve Capper1-6/+13
2013-06-07arm64: Remove __flush_dcache_page()Catalin Marinas2-7/+1
2013-06-07arm64: Do not flush the D-cache for anonymous pagesCatalin Marinas2-6/+3
2013-06-07arm64: Avoid cache flushing in flush_dcache_page()Catalin Marinas1-18/+4
2013-05-24arm64: Do not report user faults for handled signalsCatalin Marinas1-1/+2
2013-05-14arm64: mm: Fix operands of clz in __flush_dcache_allSukanto Ghosh1-1/+1
2013-05-13arm64: debug: clear mdscr_el1 instead of taking the OS lockWill Deacon1-2/+1
2013-05-08Merge tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/...Linus Torvalds1-1/+2
2013-05-08arm64: Ignore the 'write' ESR flag on cache maintenance faultsCatalin Marinas1-1/+2
2013-04-30Merge tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/...Linus Torvalds1-3/+3
2013-04-29sparse-vmemmap: specify vmemmap population range in bytesJohannes Weiner1-8/+5
2013-04-29mm/ARM: use common help functions to free reserved pagesJiang Liu1-24/+2
2013-04-25arm64: mm: Correct show_pte behaviourSteve Capper1-3/+3
2013-03-25ARM64: early_printk: Fix check for CONFIG_ARM64_64K_PAGESBen Hutchings1-1/+1
2013-02-23memory-hotplug: remove memmap of sparse-vmemmapTang Chen1-0/+3
2013-01-22arm64: Add simple earlyprintk supportCatalin Marinas1-0/+42
2012-11-23arm64: Convert empty flush_cache_{mm,page} functions to static inlineCatalin Marinas1-9/+0
2012-11-14arm64: mm: update max_dma32 before calculating size of NORMAL zoneWill Deacon1-2/+2
2012-11-14arm64: Make the user fault reporting more specificCatalin Marinas1-2/+11
2012-11-08arm64: mm: fix booting on systems with no memory below 4GBWill Deacon1-1/+1
2012-10-08arm64: Call swiotlb_init() instead of swiotlb_init_with_default_size()Catalin Marinas3-8/+4
2012-09-24arm64: Do not set the SMP/nAMP processor bitCatalin Marinas1-11/+0
2012-09-17arm64: Build infrastructureCatalin Marinas1-0/+4
2012-09-17arm64: DMA mapping APICatalin Marinas1-0/+79
2012-09-17arm64: Device specific operationsCatalin Marinas1-0/+84
2012-09-17arm64: TLB maintenance functionalityCatalin Marinas1-0/+71
2012-09-17arm64: Cache maintenance routinesCatalin Marinas2-0/+303
2012-09-17arm64: CPU supportCatalin Marinas1-0/+186
2012-09-17arm64: Process managementCatalin Marinas1-0/+159
2012-09-17arm64: MMU fault handling and page table managementCatalin Marinas6-0/+785
2012-09-17arm64: MMU initialisationCatalin Marinas2-0/+832
2012-09-17arm64: Assembly macros and definitionsCatalin Marinas1-0/+55
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