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2021-06-07arm64: entry: don't instrument entry code with KCOVMark Rutland1-0/+5
2021-06-07arm64: entry: make NMI entry/exit functions staticMark Rutland1-2/+2
2021-06-07arm64: entry: split SDEI entryMark Rutland2-45/+40
2021-06-07arm64: entry: split bad stack entryMark Rutland2-5/+12
2021-06-07arm64: entry: fold el1_inv() into el1h_64_sync_handler()Mark Rutland1-10/+1
2021-06-07arm64: entry: handle all vectors with CMark Rutland3-125/+74
2021-06-07arm64: entry: template the entry asm functionsMark Rutland1-86/+27
2021-06-07arm64: entry: improve bad_mode()Mark Rutland1-15/+16
2021-06-07arm64: entry: move bad_mode() to entry-common.cMark Rutland2-25/+27
2021-06-07arm64: entry: consolidate EL1 exception returnsMark Rutland1-4/+8
2021-06-07arm64: entry: organise entry vectors consistentlyMark Rutland1-21/+21
2021-06-07arm64: entry: organise entry handlers consistentlyMark Rutland1-42/+36
2021-06-07arm64: entry: convert IRQ+FIQ handlers to CMark Rutland2-97/+104
2021-06-07arm64: entry: add a call_on_irq_stack helperMark Rutland1-0/+36
2021-06-07arm64: entry: move NMI preempt logic to CMark Rutland2-11/+10
2021-06-07arm64: entry: move arm64_preempt_schedule_irq to entry-common.cMark Rutland2-17/+20
2021-06-07arm64: entry: convert SError handlers to CMark Rutland3-16/+38
2021-06-07arm64: entry: unmask IRQ+FIQ after EL0 handlingMark Rutland2-2/+2
2021-06-07arm64: remove redundant local_daif_mask() in bad_mode()Mark Rutland1-1/+0
2021-06-03kprobes: Do not increment probe miss count in the fault handlerNaveen N. Rao1-7/+0
2021-06-03arm64: perf: Add more support on caps under sysfsShaokun Zhang1-0/+33
2021-06-01arm64: acpi: Map EFI_MEMORY_WT memory as Normal-NCWill Deacon1-5/+17
2021-06-01kprobes: Remove kprobe::fault_handlerPeter Zijlstra1-10/+0
2021-06-01arm64: perf: Convert snprintf to sysfs_emitTian Tao1-1/+1
2021-05-27arm64: scs: Drop unused 'tmp' argument to scs_{load, save} asm macrosWill Deacon2-5/+5
2021-05-27arm64: Move instruction encoder/decoder under lib/Julien Thierry2-1459/+1
2021-05-27arm64: Move aarch32 condition check functionsJulien Thierry3-99/+99
2021-05-27arm64: Move patching utilities out of instruction encoding/decodingJulien Thierry3-147/+152
2021-05-26arm64: smp: initialize cpu offset earlierMark Rutland4-16/+18
2021-05-26arm64: smp: unify task and sp setupMark Rutland1-18/+15
2021-05-26arm64: smp: remove stack from secondary_dataMark Rutland3-6/+4
2021-05-26arm64: smp: remove pointless secondary_data maintenanceMark Rutland1-2/+0
2021-05-26arm64: Check if GMID_EL1.BS is the same on all CPUsCatalin Marinas2-0/+24
2021-05-26arm64: Change the cpuinfo_arm64 member type for some sysregs to u64Catalin Marinas1-1/+1
2021-05-26arm64/sve: Skip flushing Z registers with 128 bit vectorsMark Brown2-4/+14
2021-05-26arm64/sve: Use the sve_flush macros in sve_load_from_fpsimd_state()Mark Brown1-5/+4
2021-05-26arm64/sve: Split _sve_flush macro into separate Z and predicate flushesMark Brown1-1/+2
2021-05-26arm64: stacktrace: Relax frame record alignment requirement to 8 bytesPeter Collingbourne2-2/+2
2021-05-26arm64: Change the on_*stack functions to take a size argumentPeter Collingbourne3-9/+11
2021-05-26arm64: smccc: Add support for SMCCCv1.2 extended input/output registersSudeep Holla2-0/+66
2021-05-25arm64: Rename arm64-internal cache maintenance functionsFuad Tabba13-31/+31
2021-05-25arm64: sync_icache_aliases to take end parameter instead of sizeFuad Tabba1-1/+1
2021-05-25arm64: __clean_dcache_area_poc to take end parameter instead of sizeFuad Tabba1-2/+3
2021-05-25arm64: __flush_dcache_area to take end parameter instead of sizeFuad Tabba6-23/+45
2021-05-25arm64: __inval_dcache_area to take end parameter instead of sizeFuad Tabba1-4/+1
2021-05-25arm64: Fix comments to refer to correct function __flush_icache_rangeFuad Tabba1-2/+2
2021-05-25arm64: Downgrade flush_icache_range to invalidateFuad Tabba1-3/+7
2021-05-25arm64: Apply errata to swsusp_arch_suspend_exitFuad Tabba1-1/+2
2021-05-25arm64: Implement stack trace termination recordMadhavan T. Venkataraman4-16/+32
2021-05-12sched/core: Initialize the idle task with preemption disabledValentin Schneider1-1/+0
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