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path: root/arch/arm64/include/asm/sysreg.h
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2018-01-16KVM: arm64: Emulate RAS error registers and set HCR_EL2's TERR & TEADongjiu Geng1-0/+10
2018-01-16KVM: arm64: Save/Restore guest DISR_EL1James Morse1-0/+1
2018-01-16KVM: arm64: Set an impdef ESR for Virtual-SError using VSESR_EL2.James Morse1-0/+1
2018-01-16arm64: kernel: Prepare for a DISR userJames Morse1-0/+1
2018-01-16arm64: Unconditionally enable IESB on exception entry/return for firmware-firstJames Morse1-8/+9
2018-01-16arm64: cpufeature: Detect CPU RAS ExtentionsXie XiuQi1-0/+2
2018-01-16arm64: sysreg: Move to use definitions for all the SCTLR bitsJames Morse1-2/+63
2018-01-08arm64: Add skeleton to harden the branch predictor against aliasing attacksWill Deacon1-0/+1
2018-01-08arm64: Take into account ID_AA64PFR0_EL1.CSV3Will Deacon1-0/+1
2018-01-05arm64: v8.4: Support for new floating point multiplication instructionsDongjiu Geng1-0/+1
2017-12-22arm64: limit PA size to supported rangeKristina Martsenko1-0/+8
2017-11-03arm64/sve: System register and exception syndrome definitionsDave Martin1-0/+21
2017-11-03arm64: KVM: Hide unsupported AArch64 CPU features from guestsDave Martin1-0/+3
2017-10-24Merge branch 'for-next/perf' into aarch64/for-next/coreWill Deacon1-0/+93
2017-10-18arm64: sysreg: Move SPE registers and PSB into common header filesWill Deacon1-0/+93
2017-10-11arm64: Expose support for optional ARMv8-A featuresSuzuki K Poulose1-0/+4
2017-08-09arm64: Expose DC CVAP to userspaceRobin Murphy1-0/+1
2017-07-26arm64: sysreg: Fix unprotected macro argmuent in write_sysregDave Martin1-2/+2
2017-06-22arm64: Remove a redundancy in sysreg.hStefan Traby1-2/+2
2017-06-15arm64/kvm: vgic: use SYS_DESC()Mark Rutland1-0/+8
2017-06-15arm64/kvm: sysreg: fix typo'd SYS_ICC_IGRPEN*_EL1Mark Rutland1-2/+2
2017-06-15KVM: arm64: vgic-v3: Add ICV_RPR_EL1 handlerMarc Zyngier1-0/+1
2017-06-15KVM: arm64: vgic-v3: Add misc Group-0 handlersMarc Zyngier1-0/+4
2017-06-15KVM: arm64: vgic-v3: Add ICV_IGNREN0_EL1 handlerMarc Zyngier1-0/+1
2017-06-15KVM: arm64: vgic-v3: Add ICV_BPR0_EL1 handlerMarc Zyngier1-0/+1
2017-06-15KVM: arm64: vgic-v3: Add ICV_HPPIR1_EL1 handlerMarc Zyngier1-0/+1
2017-06-15KVM: arm64: vgic-v3: Add ICV_AP1Rn_EL1 handlerMarc Zyngier1-0/+1
2017-06-06arm64: KVM: Preserve RES1 bits in SCTLR_EL2Marc Zyngier1-0/+4
2017-04-04Merge branch 'arm64/common-sysreg' of git://git.kernel.org/pub/scm/linux/kern...Catalin Marinas1-7/+155
2017-03-20arm64: v8.3: Support for weaker release consistencySuzuki K Poulose1-0/+1
2017-03-20arm64: v8.3: Support for complex number instructionsSuzuki K Poulose1-0/+1
2017-03-20arm64: v8.3: Support for Javascript conversion instructionSuzuki K Poulose1-0/+3
2017-03-09arm64: sysreg: add Set/Way sys encodingsMark Rutland1-0/+6
2017-03-09arm64: sysreg: add register encodings used by KVMMark Rutland1-0/+37
2017-03-09arm64: sysreg: add physical timer registersMark Rutland1-0/+4
2017-03-09arm64: sysreg: subsume GICv3 sysreg definitionsMark Rutland1-0/+52
2017-03-09arm64: sysreg: add performance monitor registersMark Rutland1-0/+25
2017-03-09arm64: sysreg: add debug system registersMark Rutland1-0/+23
2017-03-09arm64: sysreg: sort by encodingMark Rutland1-8/+9
2017-01-12arm64: cpufeature: Expose CPUID registers by emulationSuzuki K Poulose1-0/+4
2017-01-10arm64: cpufeature: Define helpers for sys_reg idSuzuki K Poulose1-1/+20
2017-01-10arm64: cpufeature: Don't enforce system-wide SPE capabilityWill Deacon1-0/+1
2016-12-06arm64: Work around broken .inst when defective gas is detectedMarc Zyngier1-4/+25
2016-12-02arm64: Get rid of asm/opcodes.hMarc Zyngier1-6/+10
2016-10-17arm64: sysreg: Fix use of XZR in write_sysreg_sWill Deacon1-1/+1
2016-09-09arm64: sysreg: replace open-coded mrs_s/msr_s with {read,write}_sysreg_sWill Deacon1-0/+15
2016-09-09arm64: Work around systems with mismatched cache line sizesSuzuki K Poulose1-0/+1
2016-09-09arm64: simplify sysreg manipulationMark Rutland1-10/+10
2016-09-09arm64: sysreg: allow write_sysreg to use XZRMark Rutland1-2/+6
2016-07-01arm64: trap userspace "dc cvau" cache operation on errata-affected coreAndre Przywara1-1/+1