Age | Commit message (Collapse) | Author | Files | Lines | |
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2022-02-22 | arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs | Nishanth Menon | 1 | -0/+1 | |
Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Cc: stable@vger.kernel.org Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-6-nm@ti.com | |||||
2022-01-24 | arm64: dts: ti: k3-j721s2: Move aliases to board dts | Aswath Govindraju | 1 | -22/+0 | |
Aliases are board specific and should be in board dts files. So, move aliases to board dts and trim the list to interfaces that are actually enabled. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20211223121650.26868-2-vigneshr@ti.com | |||||
2021-12-13 | arm64: dts: ti: Add initial support for J721S2 SoC | Aswath Govindraju | 1 | -0/+189 | |
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. * Chips and Media Wave521CL H.264/H.265 encode/decode engine See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20211207080904.14324-4-a-govindraju@ti.com |