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2020-03-15arm64: dts: marvell: Fix cpu compatible for AP807-quadAmit Kucheria1-4/+4
make -k ARCH=arm64 dtbs_check shows the following errors. Fix them by removing the "arm,armv8" compatible. /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9130-db.dt.yaml: cpu@0: compatible: Additional items are not allowed ('arm,armv8' was unexpected) /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9130-db.dt.yaml: cpu@0: compatible: ['arm,cortex-a72', 'arm,armv8'] is too long CHECK arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dt.yaml /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9130-db.dt.yaml: cpu@1: compatible: Additional items are not allowed ('arm,armv8' was unexpected) /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9130-db.dt.yaml: cpu@1: compatible: ['arm,cortex-a72', 'arm,armv8'] is too long /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9130-db.dt.yaml: cpu@100: compatible: Additional items are not allowed ('arm,armv8' was unexpected) /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9130-db.dt.yaml: cpu@100: compatible: ['arm,cortex-a72', 'arm,armv8'] is too long /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9130-db.dt.yaml: cpu@101: compatible: Additional items are not allowed ('arm,armv8' was unexpected) /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9130-db.dt.yaml: cpu@101: compatible: ['arm,cortex-a72', 'arm,armv8'] is too long /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9131-db.dt.yaml: cpu@0: compatible: Additional items are not allowed ('arm,armv8' was unexpected) /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9131-db.dt.yaml: cpu@0: compatible: ['arm,cortex-a72', 'arm,armv8'] is too long /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9131-db.dt.yaml: cpu@1: compatible: Additional items are not allowed ('arm,armv8' was unexpected) /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9131-db.dt.yaml: cpu@1: compatible: ['arm,cortex-a72', 'arm,armv8'] is too long /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9131-db.dt.yaml: cpu@100: compatible: Additional items are not allowed ('arm,armv8' was unexpected) /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9131-db.dt.yaml: cpu@100: compatible: ['arm,cortex-a72', 'arm,armv8'] is too long /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9131-db.dt.yaml: cpu@101: compatible: Additional items are not allowed ('arm,armv8' was unexpected) /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9131-db.dt.yaml: cpu@101: compatible: ['arm,cortex-a72', 'arm,armv8'] is too long /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9132-db.dt.yaml: cpu@0: compatible: Additional items are not allowed ('arm,armv8' was unexpected) /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9132-db.dt.yaml: cpu@0: compatible: ['arm,cortex-a72', 'arm,armv8'] is too long /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9132-db.dt.yaml: cpu@1: compatible: Additional items are not allowed ('arm,armv8' was unexpected) /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9132-db.dt.yaml: cpu@1: compatible: ['arm,cortex-a72', 'arm,armv8'] is too long /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9132-db.dt.yaml: cpu@100: compatible: Additional items are not allowed ('arm,armv8' was unexpected) /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9132-db.dt.yaml: cpu@100: compatible: ['arm,cortex-a72', 'arm,armv8'] is too long /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9132-db.dt.yaml: cpu@101: compatible: Additional items are not allowed ('arm,armv8' was unexpected) /home/amit/work/builds/build-check/arch/arm64/boot/dts/marvell/cn9132-db.dt.yaml: cpu@101: compatible: ['arm,cortex-a72', 'arm,armv8'] is too long Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-03-15arm64: dts: marvell: fix non-existed cpu referrence in armada-ap806-dual.dtsiVadym Kochan1-0/+5
armada-ap806-dual.dtsi includes armada-ap806.dtsi which describes thermal zones for 4 cpus but only cpu0 and cpu1 only exists for dual configuration, this makes dtb compilation fail. Fix it by removing thermal zone nodes for non-existed cpus for dual configuration. Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-03-15arm64: dts: marvell: build ESPRESSObin variantsTomasz Maciej Nowak1-0/+3
The commit adding ESPRESSObin variants didn't include those in Makefile to be built. Fixes: 447b8789359f ("arm64: dts: marvell: add ESPRESSObin variants") Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-03-15arm64: dts: marvell: espressobin: indicate dts versionTomasz Maciej Nowak4-2/+6
The commit introducing ESPRESSObin variants didn't specify dts version, and because of that they are treated by dtc as legacy ones. Fix that by properly specifying version in each dts. Fixes: 447b8789359f ("arm64: dts: marvell: add ESPRESSObin variants") Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-03-13arm64: dts: marvell: espressobin: add ethernet aliasTomasz Maciej Nowak1-0/+6
The maker of this board and its variants, stores MAC address in U-Boot environment. Add alias for bootloader to recognise, to which ethernet node inject the factory MAC address. Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-03-13arm64: dts: mcbin: support 2W SFP modulesRussell King1-0/+3
Allow the SFP cages to be used with 2W SFP modules. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-03-13arm64: dts: clearfog-gt-8k: set gigabit PHY reset deassert delayRussell King1-0/+1
If the mv88e6xxx DSA driver is built as a module, it causes the ethernet driver to re-probe when it's loaded. This in turn causes the gigabit PHY to be momentarily reset and reprogrammed. However, we attempt to reprogram the PHY immediately after deasserting reset, and the PHY ignores the writes. This results in the PHY operating in the wrong mode, and the copper link states down. Set a reset deassert delay of 10ms for the gigabit PHY to avoid this. Fixes: babc5544c293 ("arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal") Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-01-08arm64: dts: marvell: clearfog-gt-8k: fix switch cpu port nodeBaruch Siach1-0/+2
Explicitly set the switch cpu (upstream) port phy-mode and managed properties. This fixes the Marvell 88E6141 switch serdes configuration with the recently enabled phylink layer. Fixes: a6120833272c ("arm64: dts: add support for SolidRun Clearfog GT 8K") Reported-by: Denis Odintsov <d.odintsov@traviangames.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-12-09arm64: dts: uDPU: SFP cages support 3W modulesRussell King1-0/+2
The SFP cages are designed to support up to 3W modules, such as G.hn, G.fast and MoCA modules. Although there is no way for such modules to declare to software that they consume 3W, we document in DT that this is the designed power level for these cages. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-12-09arm64: dts: uDPU: remove i2c-fast-modeRussell King1-0/+2
The I2C bus violates the timing specifications when run in fast mode on the uDPU, so switch to 100kHz mode. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-12-09arm64: dts: uDPU: fix broken ethernetRussell King1-0/+4
The uDPU uses both ethernet controllers, which ties up COMPHY 0 for eth1 and COMPHY 1 for eth0, with no USB3 comphy. The addition of COMPHY support made the kernel override the setup by the boot loader breaking this platform by assuming that COMPHY 0 was always used for USB3. Delete the USB3 COMPHY definition at platform level, and add phy specifications for the ethernet channels. Fixes: bd3d25b07342 ("arm64: dts: marvell: armada-37xx: link USB hosts with their PHYs") Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-12-05Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds24-1242/+2463
Pull ARM Device-tree updates from Olof Johansson: "As always, the bulk of updates. Some of the news this cycle: New SoC descriptions: - Broadcom BCM2711 - Amlogic Meson A1 and G12 - Freescale S32V234 - Marvell Armada AP807/AP807-quad and CP115 - Realtek RTD1293 and RTD1296 - Rockchip RK3308 New boards and platforms: - Allwinner: NanoPi Duo2 - Amlogic: Ugoos am6 - Atmel at91: Overkiz Kizbox2/4 - Broadcom: RPi4, Luxul XWC-2000 - Marvell: New Espressobin flavor - NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and OPOS6ULDev - Renesas: Salvator-XS - Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (653 commits) ARM: dts: logicpd-torpedo: Disable USB Host arm: dts: mt6323: add keys, power-controller, rtc and codec arm64: dts: mt8183: add systimer0 device node dt-bindings: mediatek: update bindings for MT8183 systimer arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-cc arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board. arm64: dts: rockchip: Add Beelink A1 dt-bindings: ARM: rockchip: Add Beelink A1 arm64: dts: rockchip: Add RK3328 audio pipelines arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports arm64: dts: ti: k3-j721e-main: add USB controller nodes ARM: dts: aspeed-g6: Add timer description ARM: dts: aspeed: ast2600evb: Enable i2c buses ARM: dts: at91: add a dts and dtsi file for kizbox2 based boards dt-bindings: arm: at91: Document Kizbox2-2 board binding arm64: dts: meson-gx: fix i2c compatible arm64: dts: meson-gx: cec node should be disabled by default arm64: dts: meson-g12b-odroid-n2: add missing amlogic, s922x compatible arm64: dts: meson-gxm: fix gpu irq order arm64: dts: meson-g12a: fix gpu irq order ...
2019-10-09arm64: dts: armada-3720-turris-mox: add firmware nodeMarek Behún1-0/+8
Add the node representing the firmware running on the secure processor. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: add ESPRESSObin variantsTomasz Maciej Nowak5-183/+315
This commit adds dts for different variants of ESPRESSObin board: ESPRESSObin with soldered eMMC, ESPRESSObin V7, compared to prior versions some passive elements changed and ethernet ports labels positions have been reversed, ESPRESSObin V7 with soldered eMMC. Since most of elements are the same, one common dtsi is created and referenced in each dts of particular variant. Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add support for Marvell CN9132-DBGrzegorz Jaszczyk2-0/+222
Extend the support of the CN9131 with yet another additional CP115. The last number indicates how many external CP115 are used. New available interfaces: * CP2 CRYPTO-0 (disabled) * CP2 ETH-0 (SFI, problem with the SFP cage, disabled) * CP2 GPIO-1 * CP2 GPIO-2 * CP2 I2C-0 * CP2 PCIe-0 x2 * CP2 PCIe-2 x1 (disabled) * CP2 SDHCI-0 * CP2 USB3-1 (High-speed) Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add support for Marvell CN9131-DBGrzegorz Jaszczyk2-0/+203
Extend the support of the CN9130 by adding an external CP115. The last number indicates how many external CP115 are used. New available interfaces: * CP1 CRYPTO-0 (disabled) * CP1 ETH-0 (SFI, problem with the SFP cage, disabled) * CP1 GPIO-1 * CP1 GPIO-2 * CP1 I2C-0 * CP1 PCIe-0 x2 * CP1 SPI-1 * CP1 SATA-0-1 * CP1 USB3-1 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add support for Marvell CN9130-DBGrzegorz Jaszczyk2-0/+404
Add basic support for the Marvell CN9130 modular development board. It is based on a CN9130 SoC (one AP807 and one internal CP115), extended via 2xMoCi interface to possibly add up to two more external CP115 (one located on the main board and the other on the board extension). Available interfaces: * AP UART * AP eMMC * AP SDHCI (disabled) * CPO GPIO-0 * CPO GPIO-1 * CP0 CRYPTO-0 (disabled) * CP0 I2C-0 * CP0 I2C-1 * CP0 SDHCI-0 * CP0 NAND-0 * CP0 SPI-1 * CP0 ETH-0 (SFI with SFP cage not working yet, disabled) * CP0 ETH-1 (RGMII) * CP0 ETH-2 (RGMII) * CP0 SATA-0-1 * CP0 USB3-0 (High-speed only) * CP0 USB3-1 (High-speed only) * CP0 PCIe-0 x4 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add support for Marvell CN9130 SoC supportMiquel Raynal1-0/+37
A CN9130 SoC has one AP807 and one internal CP115. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add support for CP115Miquel Raynal1-0/+12
Create a DTSI file based on the CP11x one. Differences will be described in the near future. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Externalize PCIe macros from CP11x fileMiquel Raynal3-11/+16
PCIe macros are specific to CP110 and will not fit CP115 constraints. To keep the same way the files are organized, just move some macros out of the CP11x generic file and define them directly in SoC DTSI, instead of defining single addresses in the SoC DTSI and reusing them in macros. In the end: * CP11X_PCIE_MEM_BASE SoC define is dropped * CP11X_PCIEx_MEM_BASE is moved out of the generic DT to be put in the SoC files as it replaces the above definition. * As the CP11X_PCIEx_MEM_SIZE macro is also subject to change with newer SoCs, we put it in the SoC files as well. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Drop PCIe I/O ranges from CP11x fileMiquel Raynal4-21/+4
As an example, Armada 70x0 and 80x0 SoC 0xf9000000 region points to RUNIT/SPICS0 while it is referenced in the DT as PCIe I/O memory range. This shows that I/O memory has never been used/working on the old SoCs despite the region being advertised. As PCIe I/O ranges will not be supported in newer SoCs using CP11x co-processors, let's simply drop them. It is not harmful in any case as PCIe device drivers can do it all with the regular mapped memory anyway. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Prepare the introduction of CP115Miquel Raynal5-615/+627
CP110 and CP115 are almost the same in terms of features and have a very limited set of differences. Let's create an armada-cp11x.dtsi file which will be used to instantiate both CP110 and CP115 nodes. The only changes between the two armada-cp11{0,x}.dtsi files are the following naming in macros: s/CP110/CP11X/. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignmentMiquel Raynal1-4/+4
Fix this tiny typo before renaming/changing this file. Fixes: 72a3713fadfd ("arm64: dts: marvell: de-duplicate CP110 description") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add AP807-quad cache descriptionGrzegorz Jaszczyk1-0/+42
Adding appropriate entries to device-tree allows the cache description to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add AP806-quad cache descriptionGrzegorz Jaszczyk1-0/+42
Adding appropriate entries to device-tree allows the cache description to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add AP806-dual cache descriptionGrzegorz Jaszczyk1-0/+21
Adding appropriate entries to device-tree allows the cache description to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add support for AP807/AP807-quadMiquel Raynal2-0/+80
Describe AP807 and AP807-quad support. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Move clocks to AP806 specific fileMiquel Raynal2-12/+16
Regular clocks and CPU clocks are specific to AP806, move them out of the generic AP80x file so that AP807 can use its own clocks. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Prepare the introduction of AP807 based SoCsKonstantin Porotchkin2-446/+458
Prepare the support for Marvell AP807 die. This die is very similar to AP806 but uses different DDR PHY. AP807 is a major component of CN9130 SoC series. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add AP806-dual missing CPU clocksMiquel Raynal1-0/+2
CPU clocks have been added to AP806-quad but not to the -dual variant. Fixes: c00bc38354cf ("arm64: dts: marvell: Add cpu clock node on Armada 7K/8K") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: armada-3720-turris-mox: convert usb-phy to phy-supplyMarek Behún1-6/+7
Update Turris Mox device tree to use the phy-supply property of the generic PHY framework instead of the legacy usb-phy property. This is needed since it caused a regression on Turris Mox since "usb: host: xhci-plat: Prevent an abnormally restrictive PHY init skipping". Signed-off-by: Marek Behún <marek.behun@nic.cz> Fixes: eb6c2eb6c7fb ("usb: host: xhci-plat: Prevent an abnormally restrictive PHY init skipping") Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-08arm64: dts: marvell: Enumerate the first AP806 sysconMiquel Raynal1-1/+1
There are two system controllers in the AP80x, like for ap_syscon1, enumerate the first one by renaming it s/ap_syscon/ap_syscon0/. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-31arm64: dts: marvell: add DTS for Turris MoxMarek Behún2-0/+841
This adds support for the Turris Mox board from CZ.NIC. Turris Mox is as modular router based on the Armada 3720 SOC (same as EspressoBin). The basic board can be extended by different modules. If those are connected, U-Boot lets the kernel know via device-tree. Since modules can be connected in different order and some modules can be connected multiple times (up to three modules containing 8-port ethernet switch in DSA configuration can be connected) we decided against using device-tree overlays, because it got complicated rather quickly. (For example the SFP module can be connected directly to the CPU, or after a switch module. There are four cases and all would need different SFP overlay. There are two types of switch modules (8-port with pass-through and 4-port with no pass-through). For those we would again need at least 6 more overlays.) We therefore decided to put all the possibly connected devices in one device-tree and disable them by default. When U-Boot finds out which modules are connected, it fixes the loaded device-tree accordingly just before boot. By Rob Herring's suggestion we also made it so that U-Boot completely removes nodes which are disabled after this fixup. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Rob Herring <robh@kernel.org> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-31arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrlMarek Behún1-0/+5
This adds pinctrl node for the GPIO to be used as SPI chip select 1. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27arm64: dts: marvell: Add cpu clock node on Armada 7K/8KGregory CLEMENT2-1/+11
Add cpu clock node on AP Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supplyMiquel Raynal4-30/+35
Update Aramda 7k/8k DTs to use the phy-supply property of the (recent) generic PHY framework instead of the (legacy) usb-phy preperty. Both enable the supply when the PHY is enabled. The COMPHY nodes only provide SERDES lanes configuration. The power supply that is represented by the phy-supply property is just a regulator wired to the USB connector, hence the creation of connector nodes as child of the COMPHY nodes and the supply attached to it. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodesMiquel Raynal4-0/+18
Fill-in the missing PCIe phys/phy-names DT properties of Armada 7k/8k based boards. The MacchiatoBin is a bit particular as the Armada8k-PCI IP supports x4 link widths and in this case the PHY for each lane must be referenced. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodesMiquel Raynal4-0/+10
Fill-in the missing USB3 phys/phy-names DT properties of Armada 7k/8k based boards. Only update nodes actually enabling USB3 in the default (mainline) configuration. A few USB nodes are enabled but there is only USB2 working on them. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodesMiquel Raynal5-2/+55
Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k based boards. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27arm64: dts: marvell: Add CP110 COMPHY clocksMiquel Raynal1-0/+3
Declare the three clocks feeding the COMPHY block. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27arm64: dts: marvell: armada-37xx: add mailbox nodeMarek Behún1-0/+7
This adds the rWTM BIU mailbox node for communication with the secure processor. The driver already exists in drivers/mailbox/armada-37xx-rwtm-mailbox.c. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Gregory Clement <gregory.clement@bootlin.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-06-18arm64: dts: marvell: add missing #interrupt-cells propertyRussell King1-0/+2
The GPIO interrupt controllers are missing their required specified in DT. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-06-11arm64: dts: marvell: armada-7040-db: Add USB current regulatorsMiquel Raynal1-0/+28
Armada 7040-db USB ports deliver 500mA by default while they could deliver up to 900mA (usually, for USB3 devices). The board embeds a GPIO controlled regulator on each port which can be configured to deliver each amount of current. Add a vin-supply property to the USB3 Vbus nodes for this purpose. The regulator will be automatically 'enabled', ie. set to limit at 900mA instead of 500mA. Suggested-by: Alex Leibovich <alexl@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-06-03arm64: dts: armada-3720-espressobin: correct spi nodeTomasz Maciej Nowak1-17/+1
The manufacturer of this board, ships it with various SPI NOR chips and increments U-Boot bootloader version along the time. There is no way to tell which is placed on the board since no revision bump takes place. This creates two issues. The first, cosmetic. Since the NOR chip may differ, there's message on boot stating that kernel expected w25q32dw and found different one. To correct this, remove optional device-specific compatible string. Being here lets replace bogus "spi-flash" compatible string with proper one. The second is linked to partitions layout, it changed after commit: 81e7251252 ("arm64: mvebu: config: move env to the end of the 4MB boot device") in Marvells downstream U-Boot fork [1], shifting environment location to the end of boot device. Since the new boards will have U-Boot with this change, it'll lead to improper results writing or reading from these partitions. We can't tell if users will update bootloader to recent version provided on manufacturer website, so lets drop partitons layout. 1. https://github.com/MarvellEmbeddedProcessors/u-boot-marvell.git Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-06-03arm64: dts: marvell: Disable AP I2C on Armada-8040-DBKonstantin Porotchkin1-5/+2
While AP I2C bus was available to users in early revisions of the SoC, this is not the case anymore since eMMC was connected to the AP. Most users do not have access to this I2C bus so do not enable it in the board device tree. As there are three I2C buses enabled on this board, add an alias to be sure the two other buses keep their initial numbering. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [<miquel.raynal@bootlin.com>: Reword commit message, add alias] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-06-03arm64: dts: marvell: Enable AP806 thermal throttling with CPUfreqMiquel Raynal3-10/+107
Avoid critical temperatures in the AP806 by adding the relevant trip points/cooling-maps using CPUfreq as cooling device. So far, when the temperature reaches 100°C in the thermal IP of the AP806 (close enough from the 2/4 cores) an overheat interrupt is raised. The thermal core then shutdowns the system to avoid damaging the hardware. Adding CPUfreq as a cooling device could help avoiding such very critical situation. For that, we enable thermal throttling by defining, for each CPU, two trip points with the corresponding cooling 'intensity'. CPU0 and CPU1 are in the same cluster and are driven by the same clock. Same applies for CPU2 and CPU3, if available. So changing the frequency of one will also change the frequency of the other one, hence the use of two cooling devices per core. The heat map is as follow: - Below 85°C: the cluster runs at the highest frequency (e.g: 1200MHz). - Between 85°C and 95°C: there are two trip points at half (e.g: 600MHz) and a third (e.g: 400MHz) of the highest frequency. - Above 95°C the cluster runs at a quarter of the highest frequency (e.g: 300MHz). - At 100°C the platform is shutdown. Suggested-by: Omri Itach <omrii@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-06-03arm64: dts: marvell: Change core numbering in AP806 thermal-nodeMiquel Raynal1-4/+4
When adding thermal nodes, the CPUs have been named from 1 to 4 while usually everywhere else they are referred as 0-3. Let's change this to be consistent with later changes when we will use CPUfreq and CPU phandles as cooling devices to avoid inconsistencies in the nodes numbering. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-06-03arm64: dts: marvell: clearfog-gt-8k: set SFP power limitBaruch Siach1-0/+1
The Clearfog GT-8K board is capable of supplying power up to 2W to SFP modules. Make that explicit in the device-tree. Without this property current kernel does not allow SFP modules that require more than 1W. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-06-03arm64: dts: marvell: mcbin: enlarge PCI memory windowHeinrich Schuchardt1-0/+2
Running a graphics adapter on the MACCHIATObin fails due to an insufficiently sized memory window. Enlarge the memory window for the PCIe slot to 512 MiB. With the patch I am able to use a GT710 graphics adapter with 1 GB onboard memory. These are the mapped memory areas that the graphics adapter is actually using: Region 0: Memory at cc000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at c0000000 (64-bit, prefetchable) [size=128M] Region 3: Memory at c8000000 (64-bit, prefetchable) [size=32M] Region 5: I/O ports at 1000 [size=128] Expansion ROM at ca000000 [disabled] [size=512K] Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-04-21arm64: dts: clearfog-gt-8k: add wlan_disable signal hogThomas Schreiber1-1/+12
There is currently no DT binding for GPIO rfkill signals. To make mini-PCIe attached WiFi devices work, use gpio-hog to hold the wlan_disable signal de-asserted. Signed-off-by: Thomas Schreiber <tschreibe@gmail.com> [baruch: add pinctrl node; rename tag] Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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