summaryrefslogtreecommitdiffstats
path: root/arch/arm/mm/proc-v7.S
AgeCommit message (Expand)AuthorFilesLines
2013-09-05Merge branches 'debug-choice', 'devel-stable' and 'misc' into for-linusRussell King1-2/+14
2013-09-02ARM: 7823/1: errata: workaround Cortex-A15 erratum 773022Will Deacon1-1/+13
2013-08-12ARM: mm: use inner-shareable barriers for TLB and user cache operationsWill Deacon1-1/+1
2013-07-22ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2Will Deacon1-5/+6
2013-07-14arm: delete __cpuinit/__CPUINIT usage from all ARM usersPaul Gortmaker1-2/+0
2013-06-29Merge branch 'devel-stable' into for-nextRussell King1-6/+21
2013-06-24ARM: 7773/1: PJ4B: Add support for errata 4742Gregory CLEMENT1-3/+31
2013-06-17ARM: 7754/1: Fix the CPU ID and the mask associated to the PJ4BGregory CLEMENT1-2/+2
2013-06-07ARM: add Cortex-R7 Processor InfoJonathan Austin1-1/+12
2013-06-07ARM: suspend: fix CPU suspend code for !CONFIG_MMU configurationsWill Deacon1-5/+9
2013-05-02Merge branches 'devel-stable', 'entry', 'fixes', 'mach-types', 'misc' and 'sm...Russell King1-5/+21
2013-04-17ARM: 7695/1: mvebu: Enable pj4b on LPAE compilationsGregory CLEMENT1-1/+2
2013-04-03ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP insteadWill Deacon1-2/+2
2013-03-22ARM: 7678/1: Work around faulty ISAR0 register in some Krait CPUsStepan Moskovchenko1-0/+15
2013-03-22ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 registerStephen Boyd1-2/+2
2013-01-06ARM: 7614/1: mm: fix wrong branch from Cortex-A9 to PJ4bHaojian Zhuang1-0/+1
2013-01-02ARM: 7609/1: disable errata work-arounds which access secure registersRob Herring1-1/+2
2012-12-14Merge tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-0/+67
2012-11-21arm: mm: Add support for PJ4B cpu and init routinesGregory CLEMENT1-0/+67
2012-10-18ARM: 7553/1: proc-v7: Ensure correct instruction set after cpu_resetDave Martin1-1/+1
2012-09-25ARM: mm: update __v7_setup() to the new LoUIS cache maintenance APISantosh Shilimkar1-1/+1
2012-04-15ARM: 7384/1: ThumbEE: Disable userspace TEEHBR access for !CONFIG_ARM_THUMBEEJonathan Austin1-0/+12
2012-02-27ARM: 7345/1: errata: update workaround for A9 erratum #743622Will Deacon1-3/+1
2012-01-23ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guardsWill Deacon1-6/+0
2012-01-23ARM: 7295/1: cortex-a7: move proc_info out of !CONFIG_ARM_LPAE blockWill Deacon1-10/+10
2012-01-05Merge branch 'devel-stable' into for-linusRussell King1-157/+22
2012-01-05Merge branches 'fixes' and 'misc' into for-linusRussell King1-0/+11
2011-12-23ARM: 7197/1: errata: Remove SMP dependency for erratum 751472Dave Martin1-2/+4
2011-12-11ARM: 7202/1: Add Cortex-A7 proc infoPawel Moll1-0/+11
2011-12-08ARM: LPAE: MMU setup for the 3-level page table formatCatalin Marinas1-8/+17
2011-12-08ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.SCatalin Marinas1-149/+3
2011-12-06ARM: proc-*.S: place cpu_reset functions into .idmap.text sectionWill Deacon1-0/+2
2011-10-28Merge branch 'devel-stable' of http://ftp.arm.linux.org.uk/pub/linux/arm/kern...Linus Torvalds1-28/+22
2011-10-25Merge branches 'arnd-randcfg-fixes', 'debug', 'io' (early part), 'l2x0', 'p2v...Russell King1-1/+1
2011-10-01ARM: pm: let platforms select cpu_suspend supportArnd Bergmann1-1/+1
2011-09-20ARM: pm: no need to save/restore context ID registerRussell King1-7/+6
2011-09-20ARM: pm: only use preallocated page table during resumeRussell King1-16/+17
2011-09-20ARM: pm: preallocate a page table for suspend/resumeRussell King1-6/+0
2011-08-28ARM: pm: avoid writing the auxillary control register for ARMv7Russell King1-1/+3
2011-08-28ARM: pm: some ARMv7 requires a dsb in resume to ensure correctnessRussell King1-0/+1
2011-08-28ARM: 7066/1: proc-v7: disable SCTLR.TE when disabling MMUWill Deacon1-0/+1
2011-07-21ARM: Fix build errors caused by adding generic macrosRussell King1-3/+0
2011-07-07ARM: proc: add definition of cpu_reset for ARMv6 and ARMv7 coresWill Deacon1-0/+7
2011-07-07ARM: proc: add proc info for Cortex-A15MP using classic page tablesWill Deacon1-2/+18
2011-07-07ARM: proc: add Cortex-A5 proc infoPawel Moll1-0/+11
2011-07-07ARM: proc: convert v7 proc infos into a common macroPawel Moll1-43/+24
2011-07-07ARM: mm: proc-v7: Use the new processor struct macrosDave Martin1-26/+5
2011-06-24ARM: pm: ensure ARMv7 CPUs save and restore the TLS registerRussell King1-3/+7
2011-06-24ARM: pm: proc-v7: fix missing struct processor pointers for suspend codeRussell King1-3/+3
2011-06-09Revert "ARM: 6943/1: mm: use TTBR1 instead of reserved context ID"Russell King1-4/+6
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-26 07:33:08 +0000