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path: root/arch/arm/mm/cache-l2x0.c
AgeCommit message (Expand)AuthorFilesLines
2011-07-06ARM: 6987/1: l2x0: fix disabling function to avoid deadlockWill Deacon1-6/+13
2011-03-16Merge branch 'misc' into develRussell King1-14/+18
2011-03-09ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corruptiSantosh Shilimkar1-14/+18
2011-02-19ARM: 6741/1: errata: pl310 cache sync operation may be faultySrinidhi Kasagar1-0/+6
2010-10-26ARM: l2x0: Optimise the range based operationsSantosh Shilimkar1-0/+22
2010-10-26ARM: l2x0: Determine the cache sizeSantosh Shilimkar1-2/+11
2010-10-26arm: Implement l2x0 cache disable functionsThomas Gleixner1-1/+27
2010-10-26ARM: Improve the L2 cache performance when PL310 is usedCatalin Marinas1-3/+12
2010-07-29ARM: 6272/1: Convert L2x0 to use the IO relaxed operationsCatalin Marinas1-13/+13
2010-07-09ARM: 6210/1: Do not rely on reset defaults of L2X0_AUX_CTRLSascha Hauer1-2/+3
2010-05-17Merge branch 'devel-stable' into develRussell King1-0/+10
2010-05-15ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310Jason McMullan1-5/+34
2010-03-25ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4)Catalin Marinas1-0/+10
2010-02-15ARM: 5919/1: ARM: L2 : Errata 588369: Clean & Invalidate do not invalidate cl...Santosh Shilimkar1-0/+36
2010-02-15ARM: 5916/1: ARM: L2 : Add maintainace by line helper functionsSantosh Shilimkar1-10/+26
2009-12-14Merge branch 'pending-l2x0' into cacheRussell King1-21/+72
2009-12-14ARM: cache-l2x0: make better use of background cache handlingRussell King1-11/+23
2009-12-14ARM: cache-l2x0: avoid taking spinlock for every iterationRussell King1-13/+52
2009-12-03ARM: 5845/1: l2x0: check whether l2x0 already enabledSrinidhi Kasagar1-9/+16
2008-09-06[ARM] Convert asm/io.h to linux/io.hRussell King1-1/+1
2007-09-17[ARM] 4568/1: fix l2x0 cache invalidate handling of unaligned addressesRui Sousa1-1/+11
2007-07-20[ARM] 4500/1: Add locking around the background L2x0 cache operationsCatalin Marinas1-0/+6
2007-02-11[ARM] 4135/1: Add support for the L210/L220 cache controllersCatalin Marinas1-0/+104
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