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2022-11-01ARM: at91: pm: avoid soft resetting AC DLLClaudiu Beznea1-1/+6
Do not soft reset AC DLL as controller is buggy and this operation my introduce glitches in the controller leading to undefined behavior. Fixes: f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5") Depends-on: a02875c4cbd6 ("ARM: at91: pm: fix self-refresh for sama7g5") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221026124114.985876-2-claudiu.beznea@microchip.com
2022-10-11Merge tag 'pinctrl-v6.1-1' of ↵Linus Torvalds1-15/+0
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "There is nothing exciting going on, no core changes, just a few drivers and cleanups. New drivers: - Cypress CY8C95x0 chip pin control support, along with an immediate cleanup - Mediatek MT8188 SoC pin control support - Qualcomm SM8450 and SC8280XP LPASS (low power audio subsystem) pin control support - Qualcomm PM7250, PM8450 - Rockchip RV1126 SoC pin control support Improvements: - Fix some missing pins in the Armada 37xx driver - Convert Broadcom and Nomadik drivers to use PINCTRL_PINGROUP() macro - Fix some GPIO irq_chips to be immutable - Massive Qualcomm device tree binding cleanup, with more to come" * tag 'pinctrl-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (119 commits) MAINTAINERS: adjust STARFIVE JH7100 PINCTRL DRIVER after file movement pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100" pinctrl: Create subdirectory for StarFive drivers dt-bindings: pinctrl: st,stm32: Document interrupt-controller property dt-bindings: pinctrl: st,stm32: Document gpio-hog pattern property dt-bindings: pinctrl: st,stm32: Document gpio-line-names pinctrl: st: stop abusing of_get_named_gpio() pinctrl: wpcm450: Correct the fwnode_irq_get() return value check pinctrl: bcm: Remove unused struct bcm6328_pingroup pinctrl: qcom: restrict drivers per ARM/ARM64 pinctrl: bcm: ns: Remove redundant dev_err call gpio: rockchip: request GPIO mux to pinctrl when setting direction pinctrl: rockchip: add pinmux_ops.gpio_set_direction callback pinctrl: cy8c95x0: Align function names in cy8c95x0_pmxops pinctrl: cy8c95x0: Drop atomicity on operations on push_pull pinctrl: cy8c95x0: Lock register accesses in cy8c95x0_set_mux() pinctrl: sunxi: sun50i-h5: Switch to use dev_err_probe() helper pinctrl: stm32: Switch to use dev_err_probe() helper dt-bindings: qcom-pmic-gpio: Add PM7250B and PM8450 bindings pinctrl: qcom: spmi-gpio: Add compatible for PM7250B ...
2022-10-06Merge tag 'arm-soc-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-4/+0
Pull ARM SoC updates from Arnd Bergmann: "The main changes this time are for the organization of the Kconfig files, introducing per-vendor top-level options on arm64 to match those on arm32, and making the platform selection on arm32 more uniform, in particular for the remaining StrongARM platforms that still have a couple of special cases compared to the more recent ones. I also did a cleanup of the old Footbridge platform, which was the last holdout for the phys_to_dma()/dma_to_phys() interface that is now completely gone from arm32, completing work started by Christoph Hellwig" * tag 'arm-soc-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (21 commits) ARM: aspeed: Kconfig: Fix indentation ARM: Drop CMDLINE_* dependency on ATAGS ARM: Drop CMDLINE_FORCE dependency on !ARCH_MULTIPLATFORM ARM: s3c: remove orphan declarations from arch/arm/mach-s3c/devs.h pxa: Drop if with an always false condition ARM: orion: fix include path ARM: shmobile: Drop selecting SOC_BUS arm64: renesas: Drop selecting SOC_BUS ARM: disallow PCI with MMU=n again ARM: footbridge: remove custom DMA address handling MAINTAINERS: Add BCM4908 maintainer to BCMBCA entry ARM: footbridge: move isa-dma support into footbridge ARM: footbridge: remove leftover from personal-server ARM: footbridge: remove addin mode arm64: Kconfig.platforms: Group NXP platforms together arm64: Kconfig.platforms: Re-organized Broadcom menu ARM: make ARCH_MULTIPLATFORM user-visible ARM: fix XIP_KERNEL dependencies ARM: Kconfig: clean up platform selection ARM: simplify machdirs/platdirs handling ...
2022-09-03pinctrl: at91: move gpio suspend/resume calls to driver's contextClaudiu Beznea1-15/+0
Move gpio suspend/resume execution local to driver and let it execute as close as possible to the moment the machine specific PM code is executed (by setting it to .noirq member of dev_pm_ops). With this the at91_pinctrl_gpio_suspend()/at91_pinctrl_gpio_resume() calls were removed from arch/arm/mach-at91/pm.c and also a header has been removed. The patch has been checked on sama5d3_xplained, sam9x60ek, sama5d2_xplained, sama7g5ek boards. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220831135636.3176406-3-claudiu.beznea@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-31ARM: at91: pm: fix DDR recalibration when resuming from backup and self-refreshClaudiu Beznea1-4/+32
On SAMA7G5, when resuming from backup and self-refresh, the bootloader performs DDR PHY recalibration by restoring the value of ZQ0SR0 (stored in RAM by Linux before going to backup and self-refresh). It has been discovered that the current procedure doesn't work for all possible values that might go to ZQ0SR0 due to hardware bug. The workaround to this is to avoid storing some values in ZQ0SR0. Thus Linux will read the ZQ0SR0 register and cache its value in RAM after processing it (using modified_gray_code array). The bootloader will restore the processed value. Fixes: d2d4716d8384 ("ARM: at91: pm: save ddr phy calibration data to securam") Suggested-by: Frederic Schumacher <frederic.schumacher@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220826083927.3107272-4-claudiu.beznea@microchip.com
2022-08-31ARM: at91: pm: fix self-refresh for sama7g5Claudiu Beznea1-7/+17
It has been discovered that on some parts, from time to time, self-refresh procedure doesn't work as expected. Debugging and investigating it proved that disabling AC DLL introduce glitches in RAM controllers which leads to unexpected behavior. This is confirmed as a hardware bug. DLL bypass disables 3 DLLs: 2 DX DLLs and AC DLL. Thus, keep only DX DLLs disabled. This introduce 6mA extra current consumption on VDDCORE when switching to any ULP mode or standby mode but the self-refresh procedure still works. Fixes: f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5") Suggested-by: Frederic Schumacher <frederic.schumacher@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Cristian Birsan <cristian.birsan@microchip.com> Link: https://lore.kernel.org/r/20220826083927.3107272-3-claudiu.beznea@microchip.com
2022-08-18ARM: remove obsolete Makefile.boot infrastructureArnd Bergmann1-4/+0
There are a number of old Makefile.boot files that remain from the multiplatform conversion, and three that are still in use. These provide the "ZRELADDR", "PARAMS_PHYS" and "INITRD_PHYS" values that are platform specific. It turns out that we can generally just derive this from information that is available elsewhere: - ZRELADDR is normally detected at runtime with the CONFIG_AUTO_ZRELADDR flag, but also needed to be passed to for 'make uImage'. In a multiplatform kernel, one always has to pass this as the $(LOADADDR) variable, but in the StrongARM kernels we can derive it from the sum of $(CONFIG_PHYS_OFFSET) and $(TEXT_OFFSET) that are already known. - PARAMS_PHYS and INITRD_PHYS are only used for bootpImage, which in turn is only used for the pre-ATAGS 'param_struct' based boot interface on StrongARM based machines with old boot loaders. They can both be derived from CONFIG_PHYS_OFFSET and a machine specific offset for the initrd, so all of the logic for these can be part of arch/arm/boot/bootp/Makefile. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-08-02Merge tag 'arm-soc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds3-1/+22
Pull ARM SoC updates from Arnd Bergmann: "The updates for arch/arm/mach-* platform code this time are mainly minor cleanups. Most notably, the DaVinci DM644x/DM646x SoC support gets removed. This was also scheduled for later removal early next year, but Linus Walleij asked for having them removed earlier to avoid problems for the GPIO subsystem" * tag 'arm-soc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits) ARM: at91: setup outer cache .write_sec() callback if needed ARM: at91: add sam_linux_is_optee_available() function ARM: Marvell: Update PCIe fixup ARM: bcmbca: Include full family name in Kconfig ARM: bcm: NSP: Removed forced thermal selection ARM: debug: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA arm: bcmbca: Add BCMBCA sub platforms arm: bcmbca: Move BCM63138 ARCH_BCM_63XX to ARCH_BCMBCA MAINTAINERS: Move BCM63138 to bcmbca arch entry ARM: shmobile: rcar-gen2: Increase refcount for new reference ARM: davinci: Delete DM646x board files ARM: davinci: Delete DM644x board files firmware: xilinx: Add TF_A_PM_REGISTER_SGI SMC call cpufreq: zynq: Fix refcount leak in zynq_get_revision ARM: OMAP2+: Kconfig: Fix indentation ARM: OMAP2+: Fix refcount leak in omap3xxx_prm_late_init ARM: OMAP2+: pdata-quirks: Fix refcount leak bug ARM: OMAP2+: display: Fix refcount leak bug ARM: OMAP2+: Fix refcount leak in omapdss_init_of ARM: imx25: support silicon revision 1.2 ...
2022-07-20ARM: at91: setup outer cache .write_sec() callback if neededClément Léger1-1/+15
When running under OP-TEE, the L2 cache is configured by OP-TEE and the sam platform code does not allow any modification yet. Setup a dummy .write_sec() callback to avoid triggering exceptions when Linux tries to modify the L2 cache configuration. Signed-off-by: Clément Léger <clement.leger@bootlin.com> [claudiu.beznea: keep .init_early populated only for SAMA5D2, remove sam_secure_init() from sama5d2_init() as it is also called in sama5_secure_cache_init()] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220606145701.185552-3-clement.leger@bootlin.com
2022-07-20ARM: at91: add sam_linux_is_optee_available() functionClément Léger2-0/+7
Add sam_linux_is_optee_available() which allows to know if OP-TEE is available for Linux. This function is used by code which needs to know if we running with OP-TEE available or not. Signed-off-by: Clément Léger <clement.leger@bootlin.com> [claudiu.beznea: edit commit title and message, renamed sam_linux_is_in_normal_world() into sam_linux_is_optee_available()] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220606145701.185552-2-clement.leger@bootlin.com
2022-06-28ARM: at91: pm: Mark at91_pm_secure_init as __initFabio Estevam1-1/+1
at91_pm_secure_init() is used inside sama5d2_pm_init(), which has the __init notation. Pass the __init notation to at91_pm_secure_init() as well to fix the following section mismatch warning: WARNING: modpost: vmlinux.o(.text.unlikely+0x2138): Section mismatch in reference from the function at91_pm_secure_init() to the (unknown reference) .init.rodata:(unknown) Fixes: f2f5cf78a333 ("ARM: at91: pm: add support for sama5d2 secure suspend") Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220622114810.1186330-1-festevam@gmail.com
2022-06-28ARM: at91: pm: use proper compatibles for sama7g5's rtc and rttClaudiu Beznea1-2/+2
Use proper compatible strings for SAMA7G5's RTC and RTT IPs. These are necessary for configuring wakeup sources for ULP1 PM mode. Fixes: 6501330f9f5e ("ARM: at91: pm: add pm support for SAMA7G5") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220523092421.317345-4-claudiu.beznea@microchip.com
2022-06-28ARM: at91: pm: use proper compatibles for sam9x60's rtc and rttClaudiu Beznea1-2/+2
Use proper compatible strings for SAM9X60's RTC and RTT IPs. These are necessary for configuring wakeup sources for ULP1 PM mode. Fixes: eaedc0d379da ("ARM: at91: pm: add ULP1 support for SAM9X60") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220523092421.317345-3-claudiu.beznea@microchip.com
2022-06-28ARM: at91: pm: use proper compatible for sama5d2's rtcClaudiu Beznea1-1/+1
Use proper compatible strings for SAMA5D2's RTC IPs. This is necessary for configuring wakeup sources for ULP1 PM mode. Fixes: d7484f5c6b3b ("ARM: at91: pm: configure wakeup sources for ULP1 mode") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220523092421.317345-2-claudiu.beznea@microchip.com
2022-05-27Merge tag 'at91-soc-5.19-2' of ↵Arnd Bergmann1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/late AT91 SoC #2 for 5.19: - One Kconfig fix for random build error * tag 'at91-soc-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: at91: pm: Fix rand build error Link: https://lore.kernel.org/r/20220517150832.89451-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-26Merge tag 'arm-multiplatform-5.19-1' of ↵Linus Torvalds1-1/+2
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARMv4T/v5 multiplatform support from Arnd Bergmann: "This series has been 12 years in the making, it mostly finishes the work that was started with the founding of Linaro to clean up platform support in the kernel. The largest change here is a cleanup of the omap1 platform, which is the final ARM machine type to get converted to the common-clk subsystem. All the omap1 specific drivers are now made independent of the mach/*.h headers to allow the platform to be part of a generic ARMv4/v5 multiplatform kernel. The last bit that enables this support is still missing here while we wait for some last dependencies to make it into the mainline kernel through other subsystems. The s3c24xx, ixp4xx, iop32x, ep93xx and dove platforms were all almost at the point of allowing multiplatform kernels, this work gets completed here along with a few additional cleanup. At the same time, the s3c24xx and s3c64xx are now deprecated and expected to get removed in the future. The PXA and OMAP1 bits are in a separate branch because of dependencies. Once both branches are merged, only the three Intel StrongARM platforms (RiscPC, Footbridge/NetWinder and StrongARM1100) need separate kernels, and there are no plans to include these" * tag 'arm-multiplatform-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (61 commits) ARM: ixp4xx: Consolidate Kconfig fixing issue ARM: versatile: Add missing of_node_put in dcscb_init ARM: config: Refresh IXP4xx config after multiplatform ARM: omap1: add back omap_set_dma_priority() stub ARM: omap: fix missing declaration warnings ARM: omap: fix address space warnings from sparse ARM: spear: remove include/mach/ subdirectory ARM: davinci: remove include/mach/ subdirectory ARM: omap2: remove include/mach/ subdirectory integrator: remove empty ap_init_early() ARM: s3c: fix include path MAINTAINERS: omap1: Add Janusz as an additional maintainer ARM: omap1: htc_herald: fix typos in comments ARM: OMAP1: fix typos in comments ARM: OMAP1: clock: Remove noop code ARM: OMAP1: clock: Remove unused code ARM: OMAP1: clock: Fix UART rate reporting algorithm ARM: OMAP1: clock: Fix early UART rate issues ARM: OMAP1: Prepare for conversion of OMAP1 clocks to CCF ARM: omap1: fix build with no SoC selected ...
2022-05-17ARM: at91: pm: Fix rand build errorYueHaibing1-1/+1
If ATMEL_PM is y but PM is n, build fails: arch/arm/mach-at91/pm.c:1435:13: error: redefinition of 'at91rm9200_pm_init' void __init at91rm9200_pm_init(void) ^~~~~~~~~~~~~~~~~~ In file included from arch/arm/mach-at91/pm.c:29:0: arch/arm/mach-at91/generic.h:19:27: note: previous definition of 'at91rm9200_pm_init' was here static inline void __init at91rm9200_pm_init(void) { } ^~~~~~~~~~~~~~~~~~ ATMEL_PM should not be enabled independently, it is only selected by Soc. Fixes: f2f5cf78a333 ("ARM: at91: pm: add support for sama5d2 secure suspend") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220517031606.11628-1-yuehaibing@huawei.com Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-12ARM: at91: pm: add support for sama5d2 secure suspendClément Léger3-1/+50
When running with OP-TEE, the suspend control is handled securely. Suspend can be entered using PSCI support. Since the sama5d2 supports multiple suspend modes, add a new CONFIG_ATMEL_SECURE_PM which will send a SMC call to select the suspend mode at init time. "atmel.pm_modes" boot argument is still supported for compatibility purposes but the standby value is actually ignored since PSCI suspend is used and it only support one mode (suspend). Signed-off-by: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-12ARM: at91: add code to handle secure callsClément Léger4-1/+63
Since OP-TEE now has a more complete support for sama5d2, add necessary code to perform SMC calls. The detection of OP-TEE is based on a specific device-tree node path (/firmware/optee) such has done by some other SoC. A check is added to avoid doing SMC calls without having OP-TEE. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-12ARM: at91: Kconfig: implement PIT64B selectionClaudiu Beznea1-0/+9
Implement PIT64B selection thus it will be available for the necessary targets (at the moment SAM9X60 and SAMA7G5) w/o the necessity to specify it via defconfig. With this the current CONFIG_TIMER_OF dependency of PIT64B driver could be removed. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-12ARM: at91: pm: add quirks for pmClaudiu Beznea1-2/+302
SoCs supporting ULP0 or ULP1 modes and variants of Cadence Ethernet IP (controlled by macb driver) may behave buggy when Wake-on-Lan (WoL) is configured and WoL packet is received while in ULP0/ULP1. On some SoCs Ethernet interface is not working after resume. On other SoCs the CPU goes to abort on resume path when switching execution from internal SRAM to DRAM. For ULP1 + WoL the issue is related a particular restart sequence of the internal clocks when resuming. These clocks are automatically managed by PMC and may happen that GMAC peripheral clock is restarted few clock cycles before internal clocks causing blocking of Ethernet's DMA. As a consequence Ethernet TX transactions are stopped and RX transactions are partially stopped (packets are received by MAC, RX counters incremented but the data is not transferred to DRAM). The workaround for this is to disable Ethernet's peripheral clock when going to ULP1. Same behavior has been reproduced on ULP0 for some platforms (SAMA5D2, SAMA5D3) and the same workaround solves the issue. The problem has been solved on pm.c as quirk to avoid polluting the MACB driver with AT91 specific issues as this driver is generic to multiple vendors. At probe pointers to struct device_node are retrieved and on the at91_pm_enter() the quirk specifics are applied: for all Ethernet interfaces that were parsed the peripheral clocks are disabled. A special handling is done for modes in dns_modes mask as these are considered modes that blocks the system if WoL packet are received but for which applying quirk will lead to not waking up on WoL packets: in situation where Ethernet interface(s) has suspend mode in dns_modes mask and Ethernet interface(s) is the only available wakeup source the suspend is canceled. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-12ARM: at91: pm: use kernel documentation styleClaudiu Beznea1-3/+3
Use kernel documentation style. Along with it fix the naming of struct at91_pm_sfrbu_regs in documentation. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-12ARM: at91: pm: introduce macros for pm mode replacementClaudiu Beznea1-27/+56
Introduce macros to replace standby/suspend mode if they depends on controllers that failed to map (or other errors). Macros keep track of the complementary mode to avoid having set the same AT91 PM mode for both suspend and standby. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-12ARM: at91: pm: keep documentation inline with structure membersClaudiu Beznea1-1/+1
Move documentation of bu to keep the same order as in the structure itself. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-04-08ARM: rework endianess selectionArnd Bergmann1-1/+2
Choosing big-endian vs little-endian kernels in Kconfig has not worked correctly since the introduction of CONFIG_ARCH_MULTIPLATFORM a long time ago. The problems is that CONFIG_BIG_ENDIAN depends on ARCH_SUPPORTS_BIG_ENDIAN, which can set by any one platform in the config, but would actually have to be supported by all of them. This was mostly ok for ARMv6/ARMv7 builds, since these are BE8 and tend to just work aside from problems in nonportable device drivers. For ARMv4/v5 machines, CONFIG_BIG_ENDIAN and CONFIG_ARCH_MULTIPLATFORM were never set together, so this was disabled on all those machines except for IXP4xx. As IXP4xx can now become part of ARCH_MULTIPLATFORM, it seems better to formalize this logic: all ARMv4/v5 platforms get an explicit dependency on being either big-endian (ixp4xx) or little-endian (the rest). We may want to fix ixp4xx in the future to support both, but it does not work in LE mode at the moment. For the ARMv6/v7 platforms, there are two ways this could be handled a) allow both modes only for platforms selecting 'ARCH_SUPPORTS_BIG_ENDIAN' today, but only LE mode for the others, given that these were added intentionally at some point. b) allow both modes everwhere, given that it was already possible to build that way by e.g. selecting ARCH_VIRT, and that the list is not an accurate reflection of which platforms may or may not work. Out of these, I picked b) because it seemed slighly more logical to me. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25ARM: at91: Kconfig: select PM_OPPClaudiu Beznea1-0/+1
Select PM_OPP. This is requested for CPUFreq driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-6-claudiu.beznea@microchip.com
2022-02-25ARM: at91: PM: add cpu idle support for sama7g5Claudiu Beznea1-1/+26
Add CPU idle support for SAMA7G5. Support will make use of PMC_CPU_RATIO register to divide the CPU clock by 16 before switching it to idle and use automatic self-refresh option of DDR controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-5-claudiu.beznea@microchip.com
2022-02-25ARM: at91: ddr: fix typo to align with datasheet namingClaudiu Beznea1-2/+2
Fix typo on UDDRC_PWRCTL.SELFREF_SW bitmask to align with datasheet naming. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-4-claudiu.beznea@microchip.com
2021-12-08ARM: at91: pm: Add of_node_put() before gotoWan Jiabing1-0/+2
Fix following coccicheck warning: ./arch/arm/mach-at91/pm.c:643:1-33: WARNING: Function for_each_matching_node_and_match should have of_node_put() before goto Early exits from for_each_matching_node_and_match should decrement the node reference counter. Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211014084555.21422-1-wanjiabing@vivo.com
2021-11-03Merge tag 'soc-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-0/+9
Pull ARM SoC updates from Arnd Bergmann: "The SoC updates this time are mainly removing obsolete code from the OMAP2 platform, another step in the eternal cleanup of that platform. There are two new SoCs getting added: STMicroelectronics stm32mp13 and Microchip lan966. Both fit into existing platforms and require minimal changes here. A couple of MAINTAINER file updates relate to those changes, and update some file paths" * tag 'soc-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (28 commits) MAINTAINERS: Update BCM7XXX entry with additional patterns MAINTAINERS: add pinctrl-apple-gpio to ARM/APPLE MACHINE MAINTAINERS: Add pasemi i2c to ARM/APPLE MACHINE ARM: SPEAr: Update MAINTAINERS entries ARM: OMAP2+: Drop unused CM defines for am3 ARM: OMAP2+: Drop unused CM and SCRM defines for omap4 ARM: OMAP2+: Drop unused CM and SCRM defines for omap5 ARM: OMAP2+: Drop unused CM defines for dra7 ARM: OMAP2+: Drop unused PRM defines for am3 ARM: OMAP2+: Drop unused PRM defines for am4 ARM: OMAP2+: Drop unused PRM defines for omap4 ARM: OMAP2+: Drop unused PRM defines for omap5 ARM: OMAP2+: Drop unused PRM defines for dra7 ARM: OMAP2+: Fix comment typo ARM: OMAP2+: Fix typo in some comments ARM: at91: add basic support for new SoC family lan966 dt-bindings: arm: at91: Document lan966 pcb8291 and pcb8290 boards ARM: at91: Documentation: add lan966 family ARM: at91: Documentation: add sama7g5 family MAINTAINERS: add an entry for NXP S32G boards ...
2021-10-04ARM: at91: add basic support for new SoC family lan966Kavyasree Kotagiri1-0/+9
This patch introduces Microchip LAN966 ARMv7 based SoC family of multiport gigabit AVB/TSN-capable ethernet switches. It supports two SKUs: 4-port LAN9662 with multiprotocol processing support and 8-port LAN9668 switch. LAN966 family includes copper and serial ethernet interfaces, peripheral interfaces such as PCIe, USB, TWI, SPI, UART, QSPI, SD/eMMC, Parallel Interface (PI) as well as synchronization and trigger inputs/outputs. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> [nicolas.ferre@microchip.com: merged patches for this SoC introduction] Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210831102138.2476-1-kavyasree.kotagiri@microchip.com Link: https://lore.kernel.org/r/20211004105926.5696-5-kavyasree.kotagiri@microchip.com
2021-10-04ARM: at91: pm: preload base address of controllers in tlbClaudiu Beznea1-1/+24
In suspend/resume procedure for AT91 architecture different controllers (PMC, SHDWC, RAM, RAM PHY, SFRBU) are accessed to do the proper settings for power saving. Commit f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5") introduced the access to RAMC PHY controller for SAMA7G5. The access to this controller is done after RAMC ports are closed, thus any TLB walk necessary for RAMC PHY virtual address will fail. In the development branch this was not encountered. However, on current kernel the issue is reproducible. To solve the issue the previous mechanism of pre-loading the TLB with the RAMC PHY virtual address has been used. However, only the addition of this new pre-load breaks the functionality for ARMv5 based devices (SAM9X60). This behavior has been encountered previously while debugging this code and using the same mechanism for pre-loading address for different controllers (e.g. pin controller, the assumption being that other requested translations are replaced from TLB). To solve this new issue the TLB flush + the extension of pre-loading the rest of controllers to TLB (e.g. PMC, RAMC) has been added. The rest of the controllers should have been pre-loaded previously, anyway. Fixes: f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5") Depends-on: e42cbbe5c9a2 ("ARM: at91: pm: group constants and addresses loading") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210930154219.2214051-4-claudiu.beznea@microchip.com
2021-10-04ARM: at91: pm: group constants and addresses loadingClaudiu Beznea1-8/+9
Group constants and addresses loading. This commit prepares the field for the next one. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210930154219.2214051-3-claudiu.beznea@microchip.com
2021-09-14ARM: at91: pm: switch backup area to vbat in backup modeClaudiu Beznea1-0/+52
Backup area is now switched to VDDIN33 at boot (with the help of bootloader). When switching to backup mode we need to switch backup area to VBAT as all the other power sources are cut off. The resuming from backup mode is done with the help of bootloader, so there is no need to do something particular in Linux to restore backup area power source. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210830100927.22711-1-claudiu.beznea@microchip.com
2021-09-14ARM: at91: pm: do not panic if ram controllers are not enabledClaudiu Beznea1-16/+62
In case PM is enabled but there is no RAM controller information in DT the code will panic. Avoid such scenarios by not initializing platform specific PM code in case RAM controller is not provided via DT. Reported-by: Eugen Hristev <eugen.hristev@microchip.com> Fixes: 827de1f123ba0 ("ARM: at91: remove at91_dt_initialize and machine init_early()") Fixes: 892e1f4a3ae58 ("ARM: at91: pm: add sama7g5 ddr phy controller") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210823131915.23857-2-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add sama7g5 shdwcClaudiu Beznea1-0/+1
Add SAMA7G5 SHDWC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-25-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add pm support for SAMA7G5Claudiu Beznea3-0/+40
Add support for SAMA7G5 power management modes: standby, ulp0, ulp1, backup. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-24-claudiu.beznea@microchip.com
2021-07-19ARM: at91: sama7: introduce sama7 SoC familyEugen Hristev2-0/+33
Introduce new family of SoCs, sama7, and first SoC, sama7g5. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> [claudiu.beznea@microchip.com: keep only the sama7_dt] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-23-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add sama7g5's pmcClaudiu Beznea1-0/+6
Add SAMA7G5's PMC to compatible list. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-22-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add backup mode support for SAMA7G5Claudiu Beznea2-1/+9
Adapt at91_pm_backup_init() to work for SAMA7G5. Also, set the LPM pin to shutdown controller. This will signal to PMIC that it needs to switch to the state corresponding to backup mode. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-21-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: save ddr phy calibration data to securamClaudiu Beznea1-1/+59
The resuming from backup mode is done with the help of bootloader. The bootloader reconfigure the DDR controller and DDR PHY controller. To speed-up the resuming process save the PHY calibration data into SECURAM before suspending (securam is powered on backup mode). This data will be later used by bootloader in DDR PHY reconfiguration process. Also, in the process or recalibration the first 8 words of the memory may get corrupted. To solve this, these 8 words are saved in the securam and restored by bootloader in the process of PHY configuration. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-20-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add sama7g5 ddr phy controllerClaudiu Beznea1-6/+21
SAMA7G5 self-refresh procedure accesses also the DDR PHY registers. Adapt the code so that the at91_dt_ramc() to look also for DDR PHYs, in case it is mandatory. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-19-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add sama7g5 ddr controllerClaudiu Beznea1-3/+6
Add SAMA7G5 DDR controller to the list of DDR controller compatibles. At the moment there is no standby support. Adapt the code for this. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-18-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: wait for ddr power mode offClaudiu Beznea1-0/+5
Wait for DDR power mode off before shutting down the core. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-16-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add support for 2.5V LDO regulator controlClaudiu Beznea2-0/+30
Add support to disable/enable 2.5V LDO regulator when entering/exiting any ULP mode. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-15-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add support for MCK1..4 save/restore for ulp modesClaudiu Beznea1-0/+126
Add support for MCK1..4 save restore for ULP modes. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-14-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add self-refresh support for sama7g5Claudiu Beznea3-0/+203
Add self-refresh support for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-13-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: add support for waiting MCK1..4Claudiu Beznea1-13/+35
SAMA7G5 has 5 master clocks 0..4. MCK0 is controlled differently than MCK 1..4. MCK 1..4 should also be saved/restored in the last phase of suspend/resume. Thus, adapt wait_mckrdy to support also MCK1..4. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-10-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: s/CONFIG_SOC_SAM9X60/CONFIG_HAVE_AT91_SAM9X60_PLL/gClaudiu Beznea1-2/+2
Replace CONFIG_SOC_SAM9X60 with CONFIG_HAVE_AT91_SAM9X60_PLL as the SAM9X60's PLL is also present on SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-9-claudiu.beznea@microchip.com
2021-07-19ARM: at91: pm: avoid push and pop on stack while memory is in self-refershClaudiu Beznea1-192/+205
For the previous AT91 RAM controller and self-refresh procedure this had no side effects. However, for SAMA7G5 the self-refresh procedure doesn't allow this anymore as the RAM controller ports are closed before switching it to self-refresh. This commits prepares the code for the following ones adding self-refresh and PM support for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-8-claudiu.beznea@microchip.com
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