linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Collapse)	Author	Files	Lines
2018-09-14	ARM: dts: r9a06g032: Correct UART and add all other UARTs	Phil Edworthy	1	-3/+80
	- UART0 was missing the bus clock ("apb_pclk"). - Use recently accepted r9a06g032 and rzn1 compat strings. - Add all the other UARTs. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> [simon: updated changelog] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-06	ARM: dts: r9a06g032: Use r9a06g032-sysctrl binding definitions	Geert Uytterhoeven	1	-3/+4
	Replace the hardcoded clock indices by R9A06G032_CLK_* symbols. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-07-23	ARM: dts: Renesas R9A06G032 SMP enable method	Michel Pollet	1	-0/+2
	Add a special enable method for the second CA7 of the R9A06G032 as well as the default value for the "cpu-release-addr" property. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-07-23	ARM: dts: Renesas R9A06G032 base device tree file	Michel Pollet	1	-0/+113
	This adds the Renesas R9A06G032 bare bone support. This currently only handles the SYSCTRL block note, generic parts (gic, architected timer) and a UART. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> [simon: updated MAINTAINERS file [simon: do not use r9a06g032-sysctrl.h as it is not in the renesas tree yet] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>