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Add nodes for GPU (Mali 400) to Exynos4210 and Exynos4412. Describe the
GPU as much as possible however still few elements are missing:
1. Exynos4210 bus clock is not described in hardware manual therefore
the IP gate clock was provided,
2. Exynos4412: Not sure what to do with CLK_G3D clock responsible for
gating entire IP block (it is now being disabled as unused),
3. Regulator supplies on Trats board.
Limited testing on Odroid U3 (Exynos4412).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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The SDHCI standard, MMC host controller bindings and MMC core defines
card detect pin as active low. Therefore there is no point to invert it
twice.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
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This pin is externally pulled up, so we need to disable the SoC's
internal pull down resistor to allow it to function properly.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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This pin is externally pulled up, so we need to disable the
SoC's internal pull-down.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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This pin is externally pulled up, so we should disable the SoC's
pull down resistor in order for the interrupt to function properly.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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This pins are externally pulled up, and so we should explicitly
configure them to disable the SoC-internal pull-downs. Previously
we relied on the bootloader doing this in order to allow the buttons
to function properly.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Currently, we assume that the bootloader has correctly configured
the interrupt pin for max77693. This might not actually be the case -
so it's better to configure it explicitly.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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exynos4412-midas.dtsi is base for galaxy-s3.dtsi and n710x.dts. All of
them contain fixed regulators named "voltage-regulator-X". Their
indexes got mixed up while splitting common code in commit c769eaf7a85d
("ARM: dts: exynos: Split Trats2 DTS in preparation for Midas boards").
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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The children of regulators node do not have reg/ranges properties. Move the
children up one level, get rid of regulators node and remove
address-cells and size-cells properties. This fixes warnings for
Exynos4412 Midas family boards:
arch/arm/boot/dts/exynos4412-i9300.dtb: Warning (avoid_unnecessary_addr_size):
/regulators: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
arch/arm/boot/dts/exynos4412-i9305.dtb: Warning (avoid_unnecessary_addr_size):
/regulators: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
arch/arm/boot/dts/exynos4412-n710x.dtb: Warning (avoid_unnecessary_addr_size):
/regulators: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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"debounce-inteval" was never supported.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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The Midas boards share a lot with Trats2. Split the common parts
out of Trats2 into a common Midas DTSI and a common "Galaxy S3" DTS.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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