linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Collapse)	Author	Files	Lines
2019-11-07	ARM: dts: aspeed-g6: Add timer description	Joel Stanley	1	-0/+15
	The AST2600 has 8 32-bit timers on the APB bus. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01	ARM: dts: aspeed-g6: Add remaining UARTs	Joel Stanley	1	-0/+60
	The AST2600 has five UARTs. Add UART 1 to 4. Tested-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01	ARM: dts: aspeed-g6: Fix i2c clock source	Joel Stanley	1	-17/+17
	The upstream clock for the I2C buses is APB2. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01	ARM: dts: aspeed-g6: Describe FSI masters	Joel Stanley	1	-0/+20
	The ast2600 has two FSI masters on the APB. Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01	ARM: dts: aspeed-g6: Add pinctrl properties to MDIO nodes	Andrew Jeffery	1	-0/+8
	This way enabling the MDIO controllers automatically requests the right pinmux configuration. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01	ARM: dts: aspeed-g6: Add FMC and SPI devices	Cédric Le Goater	1	-0/+79
	Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01	ARM: dts: aspeed-g6: Add lpc devices	Brad Bishop	1	-0/+87
	Everything is the same as G5, except the devices have their own interrupt now. Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01	ARM: dts: aspeed-g6: Add VUART descriptions	Joel Stanley	1	-0/+22
	The AST2600 has two VUART devices. Reviewed-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01	ARM: dts: aspeed-g6: Add i2c buses	Joel Stanley	1	-0/+266
	The AST2600 has 16 I2C buses each with their own global IRQ line. Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01	ARM: dts: aspeed-g6: Add gpio devices	Rashmica Gupta	1	-0/+26
	The AST2600 has 208 normal GPIO pins and 36 1.8V GPIOs. Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01	ARM: dts: ast2600-evb: eMMC configuration	Andrew Jeffery	1	-2/+2
	Enable the eMMC controller and limit it to 52MHz to avoid the host controller reporting bus error conditions. Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-12	ARM: dts: aspeed: Add AST2600 pinmux nodes	Andrew Jeffery	1	-6/+1
	Add them in their own dtsi and include it in aspeed-g6.dtsi to isolate the cruft. Link: https://lore.kernel.org/r/20190911165614.31641-2-joel@jms.id.au Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-12	ARM: dts: aspeed: Add AST2600 and EVB	Joel Stanley	1	-0/+266
	The AST2600 is a new SoC by ASPEED. It contains a dual core Cortex A7 CPU and shares many periperhals with the existing AST2400 and AST2500. Link: https://lore.kernel.org/r/20190911165614.31641-1-joel@jms.id.au Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Arnd Bergmann <arnd@arndb.de>