summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/aspeed-g5.dtsi
AgeCommit message (Collapse)AuthorFilesLines
2020-05-05ARM: dts: aspeed: Change KCS nodes to v2 bindingAndrew Jeffery1-12/+12
Fixes the following warnings for both g5 and g6 SoCs: arch/arm/boot/dts/aspeed-g5.dtsi:376.19-381.8: Warning (unit_address_vs_reg): /ahb/apb/lpc@1e789000/lpc-bmc@0/kcs1@0: node has a unit name, but no reg property Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: ast2500: Add XDMA EngineEddie James1-0/+11
Add a node for the XDMA engine with all the necessary information. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: ast2500: Add SCU interrupt controllerEddie James1-0/+8
Add a node for the interrupt controller provided by the SCU. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-03-15ARM: dts: aspeed-g5: add vhub port and endpoint propertiesTao Ren1-0/+2
Add "aspeed,vhub-downstream-ports" and "aspeed,vhub-generic-endpoints" properties to describe supported number of vhub ports and endpoints. Signed-off-by: Tao Ren <rentao.bupt@gmail.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Felipe Balbi <balbi@kernel.org>
2019-12-17ARM: dts: aspeed-g5: Sort LPC child nodes by unit addressAndrew Jeffery1-5/+6
Lets try to maintain some sort of sanity. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-12-17ARM: dts: aspeed: Add reg hints to syscon childrenAndrew Jeffery1-8/+10
Fixes the following warnings: arch/arm/boot/dts/aspeed-g5.dtsi:209.28-226.6: Warning (avoid_unnecessary_addr_size): /ahb/apb/syscon@1e6e2000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/boot/dts/aspeed-g4.dtsi:156.28-172.6: Warning (avoid_unnecessary_addr_size): /ahb/apb/syscon@1e6e2000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-12-17ARM: dts: aspeed: Cleanup lpc-ctrl and snoop regsAndrew Jeffery1-3/+3
Fix the following warning: arch/arm/boot/dts/aspeed-g5.dtsi:409.27-414.8: Warning (unique_unit_address): /ahb/apb/lpc@1e789000/lpc-host@80/lpc-ctrl@0: duplicate unit-address (also used in node /ahb/apb/lpc@1e789000/lpc-host@80/lpc-snoop@0) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-12-17ARM: dts: aspeed-g5: Use recommended generic node name for SDMCAndrew Jeffery1-1/+1
The EDAC is a sub-function of the SDRAM Memory Controller. Rename the node to the appropriate generic node name. Cc: Stefan M Schaeckeler <sschaeck@cisco.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Stefan Schaeckeler <sschaeck@cisco.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-12-17ARM: dts: aspeed-g5: Move EDAC node to APBAndrew Jeffery1-7/+7
Previously the register interface was not attached to any internal bus, which is not correct - it lives on the APB. Cc: Stefan M Schaeckeler <sschaeck@cisco.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Stefan Schaeckeler <sschaeck@cisco.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-12-05Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-2/+24
Pull ARM Device-tree updates from Olof Johansson: "As always, the bulk of updates. Some of the news this cycle: New SoC descriptions: - Broadcom BCM2711 - Amlogic Meson A1 and G12 - Freescale S32V234 - Marvell Armada AP807/AP807-quad and CP115 - Realtek RTD1293 and RTD1296 - Rockchip RK3308 New boards and platforms: - Allwinner: NanoPi Duo2 - Amlogic: Ugoos am6 - Atmel at91: Overkiz Kizbox2/4 - Broadcom: RPi4, Luxul XWC-2000 - Marvell: New Espressobin flavor - NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and OPOS6ULDev - Renesas: Salvator-XS - Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (653 commits) ARM: dts: logicpd-torpedo: Disable USB Host arm: dts: mt6323: add keys, power-controller, rtc and codec arm64: dts: mt8183: add systimer0 device node dt-bindings: mediatek: update bindings for MT8183 systimer arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-cc arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board. arm64: dts: rockchip: Add Beelink A1 dt-bindings: ARM: rockchip: Add Beelink A1 arm64: dts: rockchip: Add RK3328 audio pipelines arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports arm64: dts: ti: k3-j721e-main: add USB controller nodes ARM: dts: aspeed-g6: Add timer description ARM: dts: aspeed: ast2600evb: Enable i2c buses ARM: dts: at91: add a dts and dtsi file for kizbox2 based boards dt-bindings: arm: at91: Document Kizbox2-2 board binding arm64: dts: meson-gx: fix i2c compatible arm64: dts: meson-gx: cec node should be disabled by default arm64: dts: meson-g12b-odroid-n2: add missing amlogic, s922x compatible arm64: dts: meson-gxm: fix gpu irq order arm64: dts: meson-g12a: fix gpu irq order ...
2019-11-01ARM: dts: aspeed-g5: Add SGPIO descriptionHongwei Zhang1-1/+16
Add SGPIO node to the ASPEED AST2500 device tree. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: Add "spi-max-frequency" propertyCédric Le Goater1-0/+7
Keep the FMC controller chips at a safe 50 MHz rate and use 100 MHz for the PNOR on the machines using a AST2500 SoC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: Migrate away from aspeed, g[45].* compatiblesAndrew Jeffery1-1/+1
Use the SoC-specific compatible strings instead. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-10-04arm: dts: aspeed: Add vuart aspeed,sirq-polarity-sense to aspeed-g5.dtsiOskar Senft1-0/+1
Enable auto-configuration of VUART SIRQ polarity on AST2500. Signed-off-by: Oskar Senft <osk@google.com> Link: https://lore.kernel.org/r/20190905144130.220713-3-osk@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-04ARM: dts: aspeed-g5: Fixe gpio-ranges upper limitOscar A Perez1-1/+1
According to the AST2500/AST2520 specs, these SoCs support up to 228 GPIO pins. However, 'gpio-ranges' value in 'aspeed-g5.dtsi' file is currently setting the upper limit to 220 which isn't allowing access to all their GPIOs. The correct upper limit value is 232 (actual number is 228 plus a 4-GPIO hole in GPIOAB). Without this patch, GPIOs AC5 and AC6 do not work correctly on a AST2500 BMC running Linux Kernel v4.19 Fixes: 2039f90d136c ("ARM: dts: aspeed-g5: Add gpio controller to devicetree") Signed-off-by: Oscar A Perez <linux@neuralgames.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-08-21ARM: dts: aspeed: Describe SD controllersAndrew Jeffery1-0/+28
The AST2400 and AST2500 both share the same SD controller, at the same location in the physical address space and the same hardware interrupt, with the same clock configurations. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-07-23ARM: dts: aspeed: Add SGPM pinmuxHongwei Zhang1-0/+5
Add SGPM pinmux to ast2500-pinctrl function and group, to prepare for supporting SGPIO in AST2500 SoC. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-24ARM: dts: aspeed: Add aspeed-p2a-ctrl nodePatrick Venture1-0/+5
Add a node for the aspeed-p2a-ctrl module. This node, when enabled will disable the PCI-to-AHB bridge and then allow control of this bridge via ioctls, and access via mmap. Signed-off-by: Patrick Venture <venture@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-24ARM: dts: aspeed: Rename flash-controller nodesJoel Stanley1-3/+3
The device tree compiler has started spitting out warnings about these names, insisting they be called 'spi': ../arch/arm/boot/dts/aspeed-g5.dtsi:108.35-128.5: Warning (spi_bus_bridge): /ahb/flash-controller@1e631000: node name for SPI buses should be 'spi' Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-04-05ARM: dts: aspeed: Add RTC nodeJoel Stanley1-0/+6
The ASPEED ast2400 and ast2500 both contain an on board RTC device. Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-04-05ARM: dts: aspeed-g5: Add video engineEddie James1-0/+10
Add a node to describe the video engine on the AST2500. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-04-05ARM: dts: aspeed-g5: Add resets and clocks to GFX nodeJoel Stanley1-0/+4
The ast2500 has a reset for the CRT device that must be deasserted before it can be used. Similarly it has a clock gate for a clock called D1CLK that must be set to running. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-03-08Merge tag 'edac_for_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bpLinus Torvalds1-0/+7
Pull EDAC updates from Borislav Petkov: - A new EDAC AST 2500 SoC driver (Stefan M Schaeckeler) - New i10nm EDAC driver for Intel 10nm CPUs (Qiuxu Zhuo and Tony Luck) - Altera SDRAM functionality carveout for separate enablement of RAS and SDRAM capabilities on some Altera chips. (Thor Thayer) - The usual round of cleanups and fixes And last but not least: recruit James Morse as a reviewer for the ARM side. * tag 'edac_for_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: EDAC/altera: Add separate SDRAM EDAC config EDAC, altera: Add missing of_node_put() EDAC, skx_common: Add code to recognise new compound error code EDAC, i10nm: Fix randconfig builds EDAC, i10nm: Add a driver for Intel 10nm server processors EDAC, skx_edac: Delete duplicated code EDAC, skx_common: Separate common code out from skx_edac EDAC: Do not check return value of debugfs_create() functions EDAC: Add James Morse as a reviewer dt-bindings, EDAC: Add Aspeed AST2500 EDAC, aspeed: Add an Aspeed AST2500 EDAC driver
2019-01-18EDAC, aspeed: Add an Aspeed AST2500 EDAC driverStefan M Schaeckeler1-0/+7
Add support for the Aspeed AST2500 SoC. Signed-off-by: Stefan M Schaeckeler <sschaeck@cisco.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Joel Stanley <joel@jms.id.au> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-aspeed@lists.ozlabs.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: https://lkml.kernel.org/r/1547743097-5236-2-git-send-email-schaecsn@gmx.net
2019-01-17ARM: dts: aspeed: Add KCS support for LPC BMCVijay Khemka1-1/+32
This adds the description of the four Keyboard Controller Style (KCS) IPMI communication channels present in the ASPEED BMC. They are disabled by default. Signed-off-by: Vijay Khemka <vijaykhemka@fb.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-01-17ARM: dts: aspeed: Add #interrupt-cells property to gpio controllersMark Walton1-0/+1
Allows the GPIO controller to be used as an interrupt parent. of_irq_find_parent() skips interrupt controller nodes that do not have the #interrupt-cells property. Signed-off-by: Mark Walton <mark.walton@serialtek.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-09-14ARM: dts: aspeed: Fix I2C bus warningsRob Herring1-1/+1
dtc has new checks for I2C buses. The ASpeed dts files have a node named 'i2c' which causes a false positive warning. As the node is a 'simple-bus', correct the node name to be 'bus' to fix the warnings. arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-romulus.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-ast2500-evb.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-zaius.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus Cc: Joel Stanley <joel@jms.id.au> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: linux-aspeed@lists.ozlabs.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-07-25ARM: dts: aspeed: Add coprocessor interrupt controllerBenjamin Herrenschmidt1-1/+8
Add a node for the CVIC (the coprocessor interrupt controller) and add a label to the SRAM node so it can be referenced from the board device-tree file. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-07-18ARM: dts: aspeed: Use 24MHz fixed clock for pwmLei YU1-1/+1
The aspeed pwm driver always sets the clock source to 24MHz, specify the fixed clock in device tree to make sure the driver is using the correct clock frequency to calculate the fan speed. Signed-off-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-07-16ARM: dts: aspeed: Add G5 USB Virtual HubBenjamin Herrenschmidt1-0/+15
This adds the (disabled by default) device node for the Aspeed virtual hub,a long with clocks and pinmux. This also adds the missing pinmux definition for it (the kernel driver already knows about it). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-07-16ARM: dts: aspeed: Add G5 USB host pinmuxBenjamin Herrenschmidt1-0/+8
Set the default pinmux for EHCIs so boards don't have to do it an document why it is not set for UHCI. Remove the properties from the AST2500 EVB board which are now redundant Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-06-02ARM: dts: aspeed: Fix hwrng register addressJoel Stanley1-2/+2
The register address should be the full address of the rng, not the offset from the start of the SCU. Fixes: 5daa8212c08e ("ARM: dts: aspeed: Describe random number device") Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-05-25ARM: dts: Add Aspeed SoC USB controllers to device-treeBenjamin Herrenschmidt1-0/+40
This adds the USB controllers to the DT template of the AST24xx and AST25xx SoCs. This patch doesn't enable them by default on any board specific .dts yet. This will be done when we have the necessary clock/reset and pinmux support. In the meantime though, this will work if u-boot configures things properly. For the AST2400 I only added pinmux definition for port 1 which is dual USB1/USB2. There are additional USB1 only ports that might require more work but I don't have HW to test at hand so I'm leaving that to whoever cares. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-30ARM: dts: aspeed: Describe random number deviceJoel Stanley1-0/+7
There is a random number generator that updates a register in the SCU every second. This is compatible with the timeriomem rng driver in the kernel. From the timeriomem_rng bindings: quality: estimated number of bits of true entropy per 1024 bits read from the rng. Defaults to zero which causes the kernel's default quality to be used instead. Note that the default quality is usually zero which disables using this rng to automatically fill the kernel's entropy pool. As to the recommended value for us to use: Rick Altherr <raltherr@google.com> wrote: > Quality is #bit of entropy per 1000 bits read. 100 is a > conservative value that was suggested by those in the know. Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-05Merge tag 'armsoc-dt' of ↵Linus Torvalds1-4/+21
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree updates from Arnd Bergmann: "This is the usual set of changes for device trees, with over 700 non-merged changesets. There is an ongoing set of dtc warning fixes and the usual bugfixes, cleanups and added device support. The most interesting bit as usual is support for new machines listed below: - The Allwinner H6 makes its debut with the Pine-H64 board, and we get two new machines based on its older siblings: the H5 based OrangePi Zero+ and the A64 based Teres-I Laptop from Olimex. On the 32-bit side, we add The Olimex som204 based on Allwinner A20, and the Banana Pi M2 Zero development board (based on H2). - NVIDIA adds support for Tegra194 aka "Xavier", plus their p2972 development board and p2888 CPU module. - The Nuvoton npcm750 is a BMC that was newly added, for now we only support running on the evaluation board. - STmicroelectronics stm32 gains support for the stm32mp157c and two evaluation boards. - The Toradex Colibri board family grows a few members based on the i.MX6ULL variant. - The Advantec DMS-BA16 is a Qseven module using the NXP i.MX6 family of chips. - The Phytec phyBOARD Mira is a family of industrial boards based on i.MX6. For now, four models get added. - TI am335x based PDU-001 is an industrial embedded machine used for traffic monitoring - The Aspeed platform now supports running on the BMC on the Qualcomm Centriq 2400 server - Samsung Exynos4 based Galaxy S3 is a family of mobile phones Qualcomm msm8974 based Galaxy S5 is a rather different phone made by the same company. - The Xilinx Zynq and ZynqMP platforms now gained a lot of dts file for the various boards made by Xilinx themselves, as well as the Digilent Zybo Z7. - The ARM Versatile family now supports the "IB2" interface board. - The Renesas H2 based "Stout" and the H3 based Salvator-X are more evaluation boards named after a kind of beer, as most of them are. The r8a77980 (V3H) based "Condor" apparently doesn't follow that tradition. ;-) - ROC-RK3328-CC is a simple developement board from the Libre Computer Project, based on the Rockchips RK3328 SoC - Haiku is another development board plus Qseven module based on Rockchips RK3368 and made by Theobroma Systems" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (701 commits) arm: dts: modify Nuvoton NPCM7xx device tree structure arm: dts: modify Makefile NPCM750 configuration name arm: dts: modify clock binding in NPCM750 device tree arm: dts: modify timer register size in NPCM750 device tree arm: dts: modify UART compatible name in NPCM750 device tree arm: dts: add watchdog device to NPCM750 device tree arm64: dts: uniphier: add ethernet node for PXs3 ARM: dts: uniphier: add pinctrl groups of ethernet for second instance arm: dts: kirkwood*.dts: use SPDX-License-Identifier for board using GPL-2.0+ arm: dts: kirkwood*.dts: use SPDX-License-Identifier for boards using GPL-2.0+/MIT arm: dts: kirkwood*.dts: use SPDX-License-Identifier for boards using GPL-2.0 arm: dts: armada-385-turris-omnia: use SPDX-License-Identifier arm: dts: armada-385-db-ap: use SPDX-License-Identifier arm: dts: armada-388-rd: use SPDX-License-Identifier arm: dts: armada-xp-db-xc3-24g4xg: use SPDX-License-Identifier arm: dts: armada-xp-db-dxbc2: use SPDX-License-Identifier arm: dts: armada-370-db: use SPDX-License-Identifier arm: dts: armada-*.dts: use SPDX-License-Identifier for most of the Armada based board arm: dts: armada-xp-98dx: use SPDX-License-Identifier for prestara 98d SoCs arm: dts: armada-*.dtsi: use SPDX-License-Identifier for most of the Armada SoCs ...
2018-03-14ARM: dts: aspeed: Add default memory nodeJoel Stanley1-0/+5
When we removed the inclusion of skeleton.dtsi from the device trees, we broke booting for systems with bootloaders that aren't device tre aware. This can be seen, for example, when appending the device tree blob to the kernel image. The reason booting broke was that the kernel lacked the device_type label in the memory node. Add in a default memory node wth the device_type. It can contain the memory address as the location is fixed for each SoC generation, but the size needs to be added by the bootloader or the board specific dts. Fixes: 73102d6fdc32 ("ARM: dts: aspeed: Remove skeleton.dtsi") Cc: <stable@vger.kernel.org> Reported-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-02-21ARM: dts: aspeed: Add LPC reset controller nodeJoel Stanley1-0/+10
On both the ast2400 and ast2500 SoCs, the LPC reset controller is required to bring the UARTs out of reset without waiting for the LPC reset to be deasserted. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-19ARM: dts: aspeed: Add LPC clock phandlesJoel Stanley1-0/+1
The LPC device uses LCLK. Tested-by: Lei YU <mine260309@gmail.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-19ARM: dts: aspeed-g5: Update LPC nodeJoel Stanley1-4/+3
This addresses some differences between the G5 and G4 LPC nodes that make them hard to compare. There is no functional change. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-19ARM: dts: aspeed: Add IPMI BT nodeJoel Stanley1-0/+7
The IPMI BT device part of the LPC interface and is used for communication with the host processor. Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-12-21ARM: dts: aspeed: Update license headersJoel Stanley1-1/+1
In b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") these files had the GPL-2.0 licence added automatically. Update them to be GPL 2.0+ in line with other IBM kernel contributions. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-12-21ARM: dts: aspeed: Remove skeleton.dtsiJoel Stanley1-1/+0
We don't require it for any of the ASPEED systems. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-12-21ARM: dts: aspeed: Add LPC Snoop deviceJoel Stanley1-0/+6
LPC snoop hardware on the ASPEED BMC, used for monitoring host I/O port activity. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-12-21ARM: dts: aspeed: Add PWM and tachometer nodeJoel Stanley1-0/+10
The PWM/tach unit has a clock and reset phandle. It needs both in order to function correctly. Signed-off-by: Joel Stanley <joel@jms.id.au> -- v3: Add the pwm reset phandle
2017-12-21ARM: dts: aspeed: Add clock phandle to GPIOJoel Stanley1-0/+1
This enables a feature where the driver can debounce inputs. Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-12-21ARM: dts: aspeed: Add flash controller clocksJoel Stanley1-0/+3
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-12-21ARM: dts: aspeed: Add watchdog clocksJoel Stanley1-0/+3
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-12-21ARM: dts: aspeed: Add MAC clocksJoel Stanley1-0/+2
Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-12-21ARM: dts: aspeed: Add proper clock referencesJoel Stanley1-63/+42
This device tree will break existing kernels that do not have the clk patches applied (no clocksource, as we don't know the speed of the APB clock. You can boot if you pass a lpj value on the command line, but won't have a uart). Older device trees running with the newer kernel will function as well as pre-4.16 kernels. That is, that some IP blocks (i2c, pwm/tach, adc) will not work as the kernel lacks reset controller and clock enabling. This is being changed as existing device trees use fixed-clocks in order to boot without a clk driver. The newly added clk driver provides proper clock support, including gating, so we move the device trees over to properly request clocks. The SCU compatible string is updated as the g4-scu string made it into the tree before we decided on aspeed,astX000-<ip> as the format for the strings. The old string will be removed from the bindings in a future patch. Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-12-21ARM: dts: aspeed: Add LPC and child devicesAndrew Jeffery1-10/+17
Ensure the ordering is correct and add all of the children in the SoC device trees for the ast2400 and ast2500. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-17 22:21:18 +0000