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2019-01-30ARM: dts: Kill off skeleton{64}.dtsiRob Herring1-1/+2
Remove the usage of skeleton.dtsi in the remaining dts files. It was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). This will make adding a unit-address to memory nodes easier. The main tricky part to removing skeleton.dtsi is we could end up with no /memory node at all when a bootloader depends on one being present. I hacked up dtc to check for this condition. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-03-06ARM: dts: artpec: add node for hardware crypto acceleratorNiklas Cassel1-0/+6
Add node for the hardware crypto acceleration used in the artpec6 SoC. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-03-06ARM: dts: artpec: add disabled node for PCIe endpoint modeNiklas Cassel1-0/+18
The PCIe controller in the artpec6 SoC supports both root complex and endpoint mode, however, the controller can only be used in one of the modes. Both pci nodes are disabled by default. A DTS file can enable one of them, depending on what mode it wants to run. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-03-06ARM: dts: artpec: add and utilize nbpfaxi DMA controllersNiklas Cassel1-0/+58
Add nodes for the nbpfaxi DMA controllers used in the artpec6 SoC, and start using them for the exising UARTs. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-03-06ARM: dts: artpec: add and utilize artpec6 pin controllerNiklas Cassel1-0/+34
Add node for the pin controller used in the artpec6 SoC, and start using it for the exising UARTs. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-03-06ARM: dts: artpec: migrate ethernet to stmmac bindingNiklas Cassel1-7/+35
The snps,dwc-qos-ethernet binding is still supported as a glue layer in the stmmac driver. However, since the snps,dwc-qos-ethernet binding is now deprecated, migrate to stmmac's native binding. At the same time, enable features supported by the stmmac driver, such as PTP, LPI, and an additional tx queue. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-03-06ARM: dts: artpec: remove 0x prefix from clkctrl unit addressNiklas Cassel1-1/+1
Remove 0x prefix from clkctrl unit address. This silences the following dtc warning: Warning (unit_address_format): Node /clkctrl@0xf8000000 unit name should not have leading "0x" Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-03-06ARM: dts: artpec: disable Accelerator Coherency PortNiklas Cassel1-2/+1
Accesses via 0x80000000 go through the ACP instead of using the DDR directly. Unfortunately the ACP has proven to be the cause of complete system hangs. Disabling the ACP makes these problems go away. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-20arm: boot: dts: artpec6: Remove unnecessary interrupt-parent property from ↵Surender Polsani1-3/+0
sub-nodes "interrupt-parent" property is declared in root node, so it is global to all nodes. This property is re-declared in few sub-nodes. To avoid duplication this property is removed from following sub-nodes: pmu, amba@0, amba@0/ethernet. Signed-off-by: Surender Polsani <surenderp@techveda.org> Acked-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-11-26ARM: dts: artpec: add pcie supportNiklas Cassel1-1/+28
Add PCIe support to the ARTPEC-6 SoC. This uses the existing pcie-artpec6 driver. So, all that is needed is device tree entries in the DTS. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Jesper Nilsson <jespern@axis.com>
2016-09-13ARM: dts: artpec: set irq affinity on pmu interruptsLars Persson1-0/+1
The irq affinity is required for pmu interrupts. Signed-off-by: Lars Persson <larper@axis.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-09-13ARM: dts: artpec: use optimized pl310 settingsLars Persson1-0/+7
Use the cache settings that were determined to give best performance on artpec-6 typical workloads. Signed-off-by: Lars Persson <larper@axis.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-09-13ARM: dts: artpec: use clock binding headerLars Persson1-11/+12
Use defines from the clock binding header as clock indexes. Signed-off-by: Lars Persson <larper@axis.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-04-25ARM: dts: artpec: update clock bindings in artpec6.dtsiLars Persson1-79/+20
The clock binding for the main clock controller was changed to an indexed controller style binding on request of the clk maintainers. This updates the dtsi to use the new bindings. Signed-off-by: Lars Persson <larper@axis.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-03-12ARM: dts: artpec: dual-license on artpec6.dtsiLars Persson1-3/+37
Relaxed the license on the dtsi to permit use in other projects. Signed-off-by: Lars Persson <larper@axis.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-24ARM: dts: artpeg: add Artpec-6 SoC dtsi fileLars Persson1-0/+236
Initial device tree for the Artpec-6 SoC. Signed-off-by: Lars Persson <larper@axis.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Olof Johansson <olof@lixom.net>