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2015-09-03Merge branch 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/k...Linus Torvalds1-2/+6
2015-08-27ARCv2: perf: Finally introduce HS perf unitVineet Gupta1-1/+4
2015-08-27ARCv2: perf: implement exclusion of event counting in user or kernel modeAlexey Brodkin1-0/+3
2015-08-27ARCv2: perf: Support sampling events using overflow interruptsAlexey Brodkin1-2/+6
2015-08-27ARC: perf: cap the number of counters to hardware max of 32Vineet Gupta1-2/+3
2015-08-20ARC: add/fix some comments in code - no functional changeVineet Gupta2-12/+12
2015-08-20ARC: change some branchs to jumps to resolve linkage errorsYuriy Kolerov1-3/+3
2015-08-20ARC: ensure futex ops are atomic in !LLSC configVineet Gupta1-0/+12
2015-08-20ARC: make futex_atomic_cmpxchg_inatomic() return bimodalVineet Gupta1-9/+11
2015-08-20ARC: futex cosmeticsVineet Gupta1-8/+9
2015-08-20ARC: add barriers to futex codeVineet Gupta1-11/+10
2015-08-20ARCv2: Support IO Coherency and permutations involving L1 and L2 cachesAlexey Brodkin2-0/+9
2015-08-07ARCv2: spinlock/rwlock/atomics: reduce 1 instruction in exponential backoffVineet Gupta2-4/+2
2015-08-05ARC: Make pt_regs regs unsignedVineet Gupta2-37/+37
2015-08-04ARCv2: spinlock/rwlock: Reset retry delay when starting a new spin-wait cycleVineet Gupta1-3/+3
2015-08-04ARCv2: spinlock/rwlock/atomics: Delayed retry of failed SCOND with exponentia...Vineet Gupta2-4/+338
2015-08-04ARC: LLOCK/SCOND based rwlockVineet Gupta2-10/+166
2015-08-04ARC: LLOCK/SCOND based spin_lockVineet Gupta1-7/+69
2015-08-04ARC: refactor atomic inline asm operands with symbolic namesVineet Gupta1-15/+17
2015-08-04Revert "ARCv2: STAR 9000837815 workaround hardware exclusive transactions liv...Vineet Gupta1-12/+2
2015-08-03ARCv2: Fix the peripheral address space detectionVineet Gupta1-4/+3
2015-07-27atomic: Collapse all atomic_{set,clear}_mask definitionsPeter Zijlstra1-10/+0
2015-07-27atomic: Provide atomic_{or,xor,and}Peter Zijlstra1-1/+0
2015-07-27arc: Provide atomic_{or,xor,and}Peter Zijlstra1-2/+17
2015-07-17mm: clean up per architecture MM hook header filesLaurent Dufour2-15/+1
2015-07-13ARC: make sure instruction_pointer() returns unsigned valueAlexey Brodkin1-1/+1
2015-07-09ARC: Add llock/scond to futex backendVineet Gupta1-6/+42
2015-07-09ARC: Make ARC bitops "safer" (add anti-optimization)Vineet Gupta1-26/+9
2015-07-01Merge branch 'akpm' (patches from Andrew)Linus Torvalds1-5/+7
2015-07-01Merge tag 'arc-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgup...Linus Torvalds28-928/+1502
2015-06-30arc: use for_each_sg()Akinobu Mita1-5/+7
2015-06-25Merge branch 'for-4.2/sg' of git://git.kernel.dk/linux-blockLinus Torvalds1-1/+0
2015-06-24mm: new mm hook frameworkLaurent Dufour1-0/+15
2015-06-25ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)Vineet Gupta1-0/+11
2015-06-25ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelockVineet Gupta1-2/+12
2015-06-25ARC: Reduce bitops lines of code using macrosVineet Gupta1-333/+144
2015-06-25ARCv2: barriersVineet Gupta3-4/+87
2015-06-25ARC: add smp barriers around atomics per Documentation/atomic_ops.txtVineet Gupta4-0/+89
2015-06-25ARC: add compiler barrier to LLSC based cmpxchgVineet Gupta1-4/+5
2015-06-22Merge branch 'x86-core-for-linus' of git://git.kernel.org/pub/scm/linux/kerne...Linus Torvalds1-0/+1
2015-06-22ARCv2: SMP: clocksource: Enable Global Real Time counterVineet Gupta1-0/+3
2015-06-22ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et alVineet Gupta2-0/+92
2015-06-22ARCv2: Adhere to Zero Delay loop restrictionVineet Gupta2-14/+12
2015-06-22ARCv2: MMUv4: support aliasing icache configVineet Gupta1-3/+1
2015-06-22ARCv2: MMUv4: cache programming model changesVineet Gupta2-2/+6
2015-06-22ARCv2: MMUv4: TLB programming Model changesVineet Gupta3-2/+34
2015-06-22ARCv2: STAR 9000814690: Really Re-enable interrupts to avoid deadlocksVineet Gupta1-0/+5
2015-06-22ARCv2: STAR 9000808988: signals involving Delay SlotVineet Gupta1-7/+10
2015-06-22ARCv2: Support for ARCv2 ISA and HS38x coresVineet Gupta11-4/+377
2015-06-22ARCv2: [intc] HS38 core interrupt controllerVineet Gupta2-0/+117
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