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When running make dt_binding_check, the xlnx,vcu-settings binding
triggers the following two warnings:
'additionalProperties' is a required property
example-0: vcu@a0041000:reg:0: [0, 2684620800, 0, 4096] is too long
Fix the binding and make the checker happy.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201202090522.251607-1-m.tretter@pengutronix.de
Signed-off-by: Rob Herring <robh@kernel.org>
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The xlnx,vcu binding comprises two adjacent register banks:
The first register bank ("vcu_slcr") contains registers for setting the
clocks of the vcu and controlling the performance monitors. The second
bank ("logicoreip") contains the configuration settings of the video codec
unit, which are set before synthesizing the bitstream.
Drivers that drive the actual video codec unit need to read the
registers from the logicoreip register bank for configuring the vcu
firmware.
As logicoreip is a too generic name for this register bank, use
"vcu-settings" as a binding name, because the register bank basically
provides the configuration settings of the VCU.
Therefore, add the vcu-settings binding to provide a syscon interface
for other drivers to read these registers.
The alternative would have been to merge the two register banks of the
xlnx,vcu binding into one register bank and make xlnx,vcu provide a
syscon interface, but that would lead to more incompatibility than
making second register bank of xlnx,vcu optional.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201109134818.4159342-3-m.tretter@pengutronix.de
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Add Device Tree binding document for logicoreIP. This logicoreIP
provides the isolation between the processing system and
programmable logic. Also provides the clock related information.
Signed-off-by: Dhaval Shah <dshah@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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