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2017-03-08ARM: dts: mvebu: Move mv98dx3236 clock bindingsChris Packham1-0/+11
Previously the coreclk binding for the 98dx3236 SoC was inherited from the armada-370/xp. This block is present in as much as it is possible to read from the register location without causing any harm. However the actual sampled at reset values are reflected in the DFX block. Moving the binding to the DFX block enables support for different clock strapping options in hardware. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-01-09devicetree: bindings: clk: mvebu: fix description for sata1 on Armada XPUwe Kleine-König1-1/+1
SATA Host 0 clock is (as correctly documented) id 15/sata0. Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org> Signed-off-by: Rob Herring <robh@kernel.org>
2016-08-12clk: mvebu: armada-39x: add clk description for supported interfacesGrzegorz Jaszczyk1-0/+2
Both SATA and second USB3.0 interface are supported in Armada-39x SoC family. Add necessary clk description, so both xhci and sata drivers can be correctly initialized. The binding documentation has also been updated accordingly. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-03clk: mvebu: add missing CESA gate clkBoris Brezillon1-0/+1
Even if not documented in the datasheet, the Armada 370 SoC can actually gate the CESA (crypto engine) clock. Add an entry in the gating_desc table to be able to reference the CESA gateclk in the crypto node. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-03-04devicetree: bindings: update DT bindings for Marvell EBU clock supportThomas Petazzoni1-1/+14
With the introduction of the Marvell Armada 39x SoC, the DT bindings for Marvell EBU clocks need to be extended. This commit include the corresponding update to the Device Tree bindings documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2014-02-17dt: Update binding information for mvebu gating clocks with Armada 380/385Thomas Petazzoni1-4/+32
Add the binding information for the gating clocks of the Armada 380 SoCs and the Armada 385 SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-17dt: Update binding information for mvebu gating clocks with Armada 375Gregory CLEMENT1-1/+30
Add the binding information for the gating clocks of the Armada 375 SoCs Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-10-08ARM: mvebu: fix gated clock documentationGregory CLEMENT1-6/+8
The gated clock documentation referred only to the Orion SoC whereas it also applied for the Armada 370/XP SoC. This commit updates the introduction text and also the list of the compatible strings. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-02-15ARM: mvebu: correct gated clock documentationJason Cooper1-1/+1
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-11-20clk: mvebu: armada 370/XP add clock gating control provider for DTGregory CLEMENT1-0/+43
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2012-11-20clk: mvebu: add clock gating control provider for DTSebastian Hesselbarth1-0/+76
This driver allows to provide DT clocks for clock gates found on Marvell Dove and Kirkwood SoCs. The clock gates are referenced by the phandle index of the corresponding bit in the clock gating control register to ease lookup in the datasheet. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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