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2019-07-16drm/amdgpu: extend AMDGPU_CTX_PRIORITY_NORMAL commentEmil Velikov1-1/+6
Currently the AMDGPU_CTX_PRIORITY_* defines are used in both drm_amdgpu_ctx_in::priority and drm_amdgpu_sched_in::priority. Extend the comment to mention the CAP_SYS_NICE or DRM_MASTER requirement is only applicable with the former. Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-16drm/amd/powerplay: add helper of smu_clk_dpm_is_enabled for smuKevin Wang2-23/+41
v2: change function name to smu_clk_dpm_is_enabled. add this helper function to check dpm clk feature is enabled. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-16drm/amd/powerplay: fix save dpm level error for smuKevin Wang1-4/+3
the save dpm level should be save previous dpm profile level, should not modified by get dpm level function. eg: default auto 1. auto -> standard ==> dpm_level = standard, save_dpm = auto. 2. standard -> auto ==> dpm_level = auto, save_dpm = standard. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-16drm/amd/powerplay: avoid double check feature enabledKevin Wang1-15/+8
the unforce_dpm_levels doesn't need to check feature enablement. because the smu_get_dpm_freq_range function has check feature logic. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-16drm/amd/powerplay: add standard profile dpm support for smuKevin Wang1-1/+1
1. the standard dpm is not support before. 2. use auto profile to adapt standard profile. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-16drm/amd/powerplay: add socclk profile dpm support.Kevin Wang1-0/+6
1.miss socclk profile support when bringup. 2.add feature check for socclk. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-16drm/amdkfd: Consistently apply noretry settingFelix Kuehling9-17/+20
Apply the same setting to SH_MEM_CONFIG and VM_CONTEXT1_CNTL. This makes the noretry param no longer KFD-specific. On GFX10 I'm not changing SH_MEM_CONFIG in this commit because GFX10 has different retry behaviour in the SQ and I don't have a way to test it at the moment. Suggested-by: Christian König <Christian.Koenig@amd.com> CC: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by : Shaoyun.liu < Shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-16drm/amd/display: return 'NULL' instead of 'false' from ↵Arnd Bergmann1-1/+1
dcn20_acquire_idle_pipe_for_layer clang complains that 'false' is a not a pointer: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:2428:10: error: expression which evaluates to zero treated as a null pointer constant of type 'struct pipe_ctx *' [-Werror,-Wnon-literal-null-conversion] return false; Changing it to 'NULL' looks like the right thing that will shut up the warning and make it easier to read, while not changing behavior. Fixes: 7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource") Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-16drm/amd/display: Support clang option for stack alignmentArnd Bergmann2-5/+19
As previously fixed for dml in commit 4769278e5c7f ("amdgpu/dc/dml: Support clang option for stack alignment") and calcs in commit cc32ad8f559c ("amdgpu/dc/calcs: Support clang option for stack alignment"), dcn20 uses an option that is not available with clang: clang: error: unknown argument: '-mpreferred-stack-boundary=4' scripts/Makefile.build:281: recipe for target 'drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.o' failed Use the same trick that we have in the other two files. Fixes: 7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-12drm/amd/powerplay: add pstate mclk(uclk) support for navi10Kevin Wang2-1/+8
add pstate mclk(uclk) support. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-12drm/amd/powerplay: fix smu clock type change miss errorKevin Wang1-2/+2
in the smu module, use the smu_xxxclk type to identify the CLK type use SMU_SCLK, SMU_MCLK to replace PP_SCLK, PP_MCLK. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-12drm/amdgpu: support key database loading for navi10Hawking Zhang5-1/+70
Starting from navi10, driver should send Key Database Load command to bootloader before loading sys_drv and sos Signed-off-by: John Clements <John.Clements@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-12drm/amdgpu: switch to macro for psp bootloader commandHawking Zhang3-4/+10
The command will be sent to psp bootloader from driver to ask psp bootloader to exerise tOS, sys_drv and kdb loading Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-11drm/amdgpu: Print out voltage in DM_PPLIBPaul Menzel1-1/+2
As the clock is already logged, also log the voltage. Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-11drm/amd/display: Add drm_audio_component support to amdgpu_dmNicholas Kazlauskas3-0/+248
[Why] The drm_audio_component can be used to give pin ELD notifications directly to the sound driver. This fixes audio endpoints disappearing due to missing unsolicited notifications. [How] Send the notification via the audio component whenever we enable or disable audio state on a stream. This matches what i915 does with their drm_audio_component and what Takashi Iwai's proposed hack for radeon/amdpgu did. This is a bit delayed in when the notification actually occurs, however. We wait until after all the programming is complete rather than sending the notification mid sequence. Particular care is needed for the get ELD callback since it can happen outside the locking and fencing DRM does for atomic commits. Cc: Leo Li <sunpeng.li@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-11drm/amd/display: Expose audio inst from DC to DMNicholas Kazlauskas2-0/+4
[Why] In order to give pin notifications to the sound driver from DM we need to know whether audio is enabled on a stream and what pin it's using from DC. [How] Expose the instance via stream status if it's a mapped resource for the stream. It will be -1 if there's no audio mapped. Cc: Leo Li <sunpeng.li@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-11drm/amdkfd: fix cp hang in evictionEric Huang1-7/+9
The cp hang occurs in OCL conformance test only on supermicro platform which has 40 cores and the test generates 40 threads. The root cause is race condition in non-protected flags. The fix is to add flags of is_evicted and is_active(init_mqd()) into protected area. Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-11drm/amdgpu: enable IP discovery by default on naviAlex Deucher1-1/+2
Use the IP discovery table rather than hardcoding the settings in the driver. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-11drm/amdgpu/discovery: fix DCE_HWIP mapping error in hw_id_map arraytiancyin1-1/+1
ID of DCE_HWIP from vbios is DMU_HWID, mismatch cause null pointer crash in navi10 modprobe. Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-11drm/amd/powerplay: bug fix for sysfsKenneth Feng1-2/+2
when we set profile_peak to sysfs:power_dpm_force_performance_level, we gets the wrong socclk level and mclk level.this patch fix this issue. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-11drm/amd/powerplay: increase the SMU msg response waiting timeEvan Quan1-1/+1
This is expected to fix some mode1 reset failures. And this affects SMU part only as the timeout setting for other parts is controlled by a different macro. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-11drm/amdgpu: Fix potential integer overflowsFelix Kuehling1-4/+5
With mm_nodes larger than 4GB, byte_count in amdgpu_fill_buffer would overflow. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-09drm/amdgpu/psp: add a mutex to protect access to the psp ringAlex Deucher3-2/+16
We need to serialize access to the psp ring if there are multiple callers at runtime. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-09drm/amdgpu/navi10: add uclk activity sensorAlex Deucher1-2/+14
Query the metrics table for the current uclk activity. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-09drm/amdgpu: properly guard the generic discovery codeAlex Deucher1-2/+2
It's only available on navi and newer. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-09drm/amdgpu: add missing documentation on new module parametersAlex Deucher1-0/+13
New parameters added for navi lack documentation. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-09drm/amdgpu: don't invalidate caches in RELEASE_MEM, only do the writebackMarek Olšák1-5/+1
This RELEASE_MEM use has the Release semantic, which means we should write back but not invalidate. Invalidations only make sense with the Acquire semantic (ACQUIRE_MEM), or when RELEASE_MEM is used to do the combined Acquire-Release semantic, which is a barrier, not a fence. The undesirable side effect of doing invalidations for the Release semantic is that it invalidates caches while shaders are running, because the Release can execute in the middle of the next IB. UMDs should use ACQUIRE_MEM at the beginning of IBs. Doing cache invalidations for a fence (like in this case) doesn't do anything for correctness. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-08drm/amd/display: avoid 64-bit divisionArnd Bergmann2-3/+3
On 32-bit architectures, dividing a 64-bit integer in the kernel leads to a link error: ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! Change the two recently introduced instances to a multiply+shift operation that is also much cheaper on 32-bit architectures. We can do that here, since both of them are really 32-bit numbers that change a few percent. Fixes: bedbbe6af4be ("drm/amd/display: Move link functions from dc to dc_link") Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for NV") Acked-by: Slava Abramov <slava.abramov@amd.com> Tested-by: Slava Abramov <slava.abramov@amd.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-08drm/amdgpu/psp11: simplify the ucode register logicAlex Deucher1-2/+2
Split it between navi10 and newer and everything before navi10. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-08drm/amdgpu: properly guard DC support in navi codeAlex Deucher1-0/+4
Need to add appropriate ifdef. Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-08drm/amd/powerplay: vega20: fix uninitialized variable useArnd Bergmann1-1/+4
If smu_get_current_rpm() fails, we can't use the output, as that may be uninitialized: drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:3023:8: error: variable 'current_rpm' is used uninitialized whenever '?:' condition is false [-Werror,-Wsometimes-uninitialized] ret = smu_get_current_rpm(smu, &current_rpm); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:735:3: note: expanded from macro 'smu_get_current_rpm' ((smu)->funcs->get_current_rpm ? (smu)->funcs->get_current_rpm((smu), (speed)) : 0) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:3024:12: note: uninitialized use occurs here percent = current_rpm * 100 / pptable->FanMaximumRpm; ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:3023:8: note: remove the '?:' if its condition is always true ret = smu_get_current_rpm(smu, &current_rpm); ^ drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:735:3: note: expanded from macro 'smu_get_current_rpm' ((smu)->funcs->get_current_rpm ? (smu)->funcs->get_current_rpm((smu), (speed)) : 0) ^ drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:3020:22: note: initialize the variable 'current_rpm' to silence this warning uint32_t current_rpm; Propagate the error code in that case. Fixes: ee0db82027ee ("drm/amd/powerplay: move PPTable_t uses into asic level") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-08drm/amd/display: dcn20: include linux/delay.hArnd Bergmann1-0/+1
Without this header, we get a compiler error in some configurations: .../dc/dcn20/dcn20_hwseq.c: In function 'dcn20_hwss_wait_for_blank_complete': .../dc/dcn20/dcn20_hwseq.c:1493:3: error: implicit declaration of function 'udelay' [-Werror=implicit-function-declaration] Note: the use of udelay itself may be problematic, as can occupy the CPU for 200ms in a busy-loop here. Fixes: 7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-08amdgpu: make pmu support optionalArnd Bergmann2-3/+7
When CONFIG_PERF_EVENTS is disabled, we cannot compile the pmu portion of the amdgpu driver: drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:48:38: error: no member named 'hw' in 'struct perf_event' struct hw_perf_event *hwc = &event->hw; ~~~~~ ^ drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:51:13: error: no member named 'attr' in 'struct perf_event' if (event->attr.type != event->pmu->type) ~~~~~ ^ ... Use conditional compilation for this file. Fixes: 9c7c85f7ea1f ("drm/amdgpu: add pmu counters") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-08drm/amd/powerplay: Zero initialize current_rpm in vega20_get_fan_speed_percentNathan Chancellor1-2/+1
clang warns (trimmed for brevity): drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:3023:8: warning: variable 'current_rpm' is used uninitialized whenever '?:' condition is false [-Wsometimes-uninitialized] ret = smu_get_current_rpm(smu, &current_rpm); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ smu_get_current_rpm expands to a ternary operator conditional on smu->funcs->get_current_rpm being not NULL. When this is false, current_rpm will be uninitialized. Zero initialize current_rpm to avoid using random stack values if that ever happens. Fixes: ee0db82027ee ("drm/amd/powerplay: move PPTable_t uses into asic level") Link: https://github.com/ClangBuiltLinux/linux/issues/588 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-08drm/amd/powerplay: Zero initialize freq in smu_v11_0_get_current_clk_freqNathan Chancellor1-1/+1
clang warns (trimmed for brevity): drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1098:10: warning: variable 'freq' is used uninitialized whenever '?:' condition is false [-Wsometimes-uninitialized] ret = smu_get_current_clk_freq_by_table(smu, clk_id, &freq); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ If get_current_clk_freq_by_table is ever NULL, freq will fail to be properly initialized. Zero initialize it to avoid using uninitialized stack values. smu_get_current_clk_freq_by_table expands to a ternary operator conditional on smu->funcs->get_current_clk_freq_by_table being not NULL. When this is false, freq will be uninitialized. Zero initialize freq to avoid using random stack values if that ever happens. Fixes: e36182490dec ("drm/amd/powerplay: fix dpm freq unit error (10KHz -> Mhz)") Link: https://github.com/ClangBuiltLinux/linux/issues/585 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-08drm/amd/powerplay: Use memset to initialize metrics structsNathan Chancellor1-2/+6
clang warns: drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:601:33: warning: suggest braces around initialization of subobject [-Wmissing-braces] static SmuMetrics_t metrics = {0}; ^ {} drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:905:26: warning: suggest braces around initialization of subobject [-Wmissing-braces] SmuMetrics_t metrics = {0}; ^ {} 2 warnings generated. One way to fix these warnings is to add additional braces like clang suggests; however, there has been a bit of push back from some maintainers[1][2], who just prefer memset as it is unambiguous, doesn't depend on a particular compiler version[3], and properly initializes all subobjects. Do that here so there are no more warnings. [1]: https://lore.kernel.org/lkml/022e41c0-8465-dc7a-a45c-64187ecd9684@amd.com/ [2]: https://lore.kernel.org/lkml/20181128.215241.702406654469517539.davem@davemloft.net/ [3]: https://lore.kernel.org/lkml/20181116150432.2408a075@redhat.com/ Fixes: 98e1a543c7b1 ("drm/amd/powerplay: add function get current clock freq interface for navi10") Fixes: ab43c4bf1cc8 ("drm/amd/powerplay: fix fan speed show error (for hwmon pwm)") Link: https://github.com/ClangBuiltLinux/linux/issues/583 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-08drm/amdgpu/mes10.1: Fix header guardNathan Chancellor1-1/+1
clang warns: In file included from drivers/gpu/drm/amd/amdgpu/nv.c:53: drivers/gpu/drm/amd/amdgpu/../amdgpu/mes_v10_1.h:24:9: warning: '__MES_V10_1_H__' is used as a header guard here, followed by #define of a different macro [-Wheader-guard] #ifndef __MES_V10_1_H__ ^~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../amdgpu/mes_v10_1.h:25:9: note: '__MES_v10_1_H__' is defined here; did you mean '__MES_V10_1_H__'? #define __MES_v10_1_H__ ^~~~~~~~~~~~~~~ __MES_V10_1_H__ 1 warning generated. Capitalize the V. Fixes: 886f82aa7a1d ("drm/amdgpu/mes10.1: add ip block mes10.1 (v2)") Link: https://github.com/ClangBuiltLinux/linux/issues/582 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-08drm/amd/powerplay: add temperature sensor support for navi10Kevin Wang1-0/+41
the hwmon interface need temperature sensor type support. 1. SENSOR_HOTSPOT_TEMP 2. SENSOR_EDGE_TEMP(SENSOR_GPU_TEMP) 3. SENSOR_MEM_TEMP Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-08drm/amdgpu: fix scheduler timeout calcFlora Cui1-4/+9
scheduler timeout is in jiffies v2: move timeout check to amdgpu_device_get_job_timeout_settings after parsing the value v3: add lockup_timeout param check. 0: keep default value. negative: infinity timeout. v4: refactor codes. Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-08drm/amdgpu: Prepare for hmm_range_register API change (v2)Philip Yang7-51/+57
An upcoming change in the hmm_range_register API requires passing in a pointer to an hmm_mirror instead of mm_struct. To access the hmm_mirror we need pass bo instead of ttm to amdgpu_ttm_tt_get_user_pages because mirror is part of amdgpu_mn structure, which is accessible from bo. v2: fix building without CONFIG_HMM_MIRROR (Arnd) Signed-off-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-05drm/amdgpu: add mode1 (psp) reset for navi asicKevin Wang1-2/+36
add mode1 (by psp) reset for navi asic. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-05drm/amdgpu: Disable ras features on all IPs before gpu resetxinhui pan1-0/+4
Perform a ras_suspend to disable ras on all IPs to workaround some ROCm stability issue. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-05drm/amd/powerplay: add baco smu reset function for smu11Kevin Wang7-3/+158
add baco reset support for smu11. it can help gpu do asic reset when gpu recovery. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-05drm/amd/powerplay: increase waiting time for smu responseJack Xiao1-3/+3
We observed some SMU commands take more time for execution, so increase waiting time for response. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-05drm/amd/powerplay/smu7_hwmgr: replace blocking delay with non-blockingYrjan Skrimstad1-1/+1
This driver currently contains a repeated 500ms blocking delay call which causes frequent major buffer underruns in PulseAudio. This patch fixes this issue by replacing the blocking delay with a non-blocking sleep call. Signed-off-by: Yrjan Skrimstad <yrjan@skrimstad.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-05drm/amdgpu: Use kmemdup rather than duplicating its implementationFuqian Huang4-13/+7
kmemdup is introduced to duplicate a region of memory in a neat way. Rather than kmalloc/kzalloc + memcpy, which the programmer needs to write the size twice (sometimes lead to mistakes), kmemdup improves readability, leads to smaller code and also reduce the chances of mistakes. Suggestion to use kmemdup rather than using kmalloc/kzalloc + memcpy. Reviewed-by: Christian König <Christian.Koenig@amd.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: Fuqian Huang <huangfq.daxian@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-03drm/amdkfd: Disable idle optimization for chained runlistFelix Kuehling1-0/+1
This works around difficult-to-reproduce soft hangs on oversubscribed runlists. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-03drm/amdkfd: Add chained_runlist_idle_disable flag to pm4_mes_runlistFelix Kuehling1-1/+1
New flag to disable an idle runlist optimization that is causing soft hangs with some diffult-to-reproduce customer workloads. This will serve as a workaround until the problem can be reproduced and the root-cause determined. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-03drm/amdgpu: Fix tracking of invalid userptrsFelix Kuehling1-0/+6
Restore the code that resets mem->invalid. Othewise so mapping userptrs after they got an MMU notifiers would always be skipped. This also avoids unnecessarily calling get_user_pages on BOs that have not been invalidated since the last try. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-03drm/amdgpu: Use FENCE_OWNER_KFD in process_sync_pds_resvFelix Kuehling1-1/+1
We don't want eviction fences to trigger when waiting for page table updates to complete during restore. In theory there shouldn't be any unsignaled eviction fences in the PD reservation object, but I'm seeing them in instrumented code for reasons not fully understood. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-19 15:04:58 +0000