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2019-02-28mmc: core: Add discard support to sdAvri Altman3-5/+14
SD spec v5.1 adds discard support. The flows and commands are similar to mmc, so just set the discard arg in CMD38. A host which supports DISCARD shall check if the DISCARD_SUPPORT (b313) is set in the SD_STATUS register. If the card does not support discard, the host shall not issue DISCARD command, but ERASE command instead. Post the DISCARD operation, the card may de-allocate the discarded blocks partially or completely. So the host mustn't make any assumptions concerning the content of the discarded region. This is unlike ERASE command, in which the region is guaranteed to contain either '0's or '1's, depends on the content of DATA_STAT_AFTER_ERASE (b55) in the scr register. One more important difference compared to ERASE is the busy timeout which we will address on the next patch. Signed-off-by: Avri Altman <avri.altman@wdc.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-28mmc: sdhci-esdhc-imx: clear the HALT bit when enable CQEBOUGH CHEN1-0/+13
After system suspend, CQE is in cqhci_off state, which set the HALT bit, make CQE in HALT state. If the SoC do not power down the USDHC module, then when system resume back, this bit keep the same, still set. Though there is a sdhci reset during sdhci_resume_host(), but this reset do not impact the CQE part, so need to clear this bit when enable CQE, otherwise CQE will stuck in the first CMDQ request after system resume back. Find this issue on NXP i.MX845s-mek board [ 105.919862] mmc2: cqhci: timeout for tag 6 [ 105.923965] mmc2: cqhci: ============ CQHCI REGISTER DUMP =========== [ 105.930407] mmc2: cqhci: Caps: 0x0000310a | Version: 0x00000510 [ 105.936847] mmc2: cqhci: Config: 0x00001001 | Control: 0x00000001 [ 105.943286] mmc2: cqhci: Int stat: 0x00000000 | Int enab: 0x00000006 [ 105.949725] mmc2: cqhci: Int sig: 0x00000006 | Int Coal: 0x00000000 [ 105.956164] mmc2: cqhci: TDL base: 0x7809b000 | TDL up32: 0x00000000 [ 105.962604] mmc2: cqhci: Doorbell: 0x00000040 | TCN: 0x00000000 [ 105.969043] mmc2: cqhci: Dev queue: 0x00000000 | Dev Pend: 0x00000000 [ 105.975483] mmc2: cqhci: Task clr: 0x00000000 | SSC1: 0x00011000 [ 105.981922] mmc2: cqhci: SSC2: 0x00000001 | DCMD rsp: 0x00000000 [ 105.988362] mmc2: cqhci: RED mask: 0xfdf9a080 | TERRI: 0x00000000 [ 105.994801] mmc2: cqhci: Resp idx: 0x00000000 | Resp arg: 0x00000000 [ 106.001240] mmc2: sdhci: ============ SDHCI REGISTER DUMP =========== [ 106.007680] mmc2: sdhci: Sys addr: 0xb2b37800 | Version: 0x00000002 [ 106.014120] mmc2: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000001 [ 106.020560] mmc2: sdhci: Argument: 0x00010000 | Trn mode: 0x00000013 [ 106.026999] mmc2: sdhci: Present: 0x01f88008 | Host ctl: 0x00000030 [ 106.033439] mmc2: sdhci: Power: 0x00000002 | Blk gap: 0x00000080 [ 106.039878] mmc2: sdhci: Wake-up: 0x00000008 | Clock: 0x0000000f [ 106.046318] mmc2: sdhci: Timeout: 0x0000008f | Int stat: 0x00000000 [ 106.052757] mmc2: sdhci: Int enab: 0x107f4000 | Sig enab: 0x107f4000 [ 106.059196] mmc2: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000502 [ 106.065635] mmc2: sdhci: Caps: 0x07eb0000 | Caps_1: 0x8000b407 [ 106.072075] mmc2: sdhci: Cmd: 0x00000d1a | Max curr: 0x00ffffff [ 106.078514] mmc2: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0x31360181 [ 106.084954] mmc2: sdhci: Resp[2]: 0x44473430 | Resp[3]: 0x00450100 [ 106.091392] mmc2: sdhci: Host ctl2: 0x00000008 [ 106.095836] mmc2: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x7804b208 [ 106.102274] mmc2: sdhci: ============================================ [ 106.108785] mmc2: running CQE recovery Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-28mmc: core: do not retry CMD6 in __mmc_switch()Chaotian Jing1-1/+1
the response type of CMD6 is R1B, when the first CMD6 gets response CRC error, do retry may get timeout error due to card may still in busy state, which cause this retry make no sense. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: core: Convert mmc_align_data_size() into an SDIO specific functionUlf Hansson3-36/+21
The only user of mmc_align_data_size() is sdio_align_size(), which is called from SDIO func drivers to let them distinguish, how to optimally allocate data buffers. Let's move mmc_align_data_size() close to the SDIO code as to make it static, rename it to _sdio_align_size() and simplify its definition, all with the purpose of clarifying that this is SDIO specific. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Avri Altman <avri.altman@wdc.com>
2019-02-25mmc: core: Move mmc_of_parse_voltage() to host.cUlf Hansson2-48/+44
MMC OF parsing functions, which parses various host DT properties, should stay close to each other. Therefore, let's move mmc_of_parse_voltage() close to mmc_of_parse() into host.c. Additionally, there is no reason to build the code only when CONFIG_OF is set, as there should be stub functions for the OF helpers that is being used, so let's drop this condition as well. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: core: Convert mmc_regulator_get_ocrmask() to staticUlf Hansson2-8/+1
The only left user of mmc_regulator_get_ocrmask() is the mmc core itself. Therefore, let's drop the export and turn it into static. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: core: Move regulator helpers to separate fileUlf Hansson5-244/+263
The mmc regulator helper functions, are placed in the extensive core.c file. In a step towards trying to create a better structure of files, avoiding too many lines of code per file, let's move these helpers to a new file, regulator.c. Moreover, this within this context it makes sense to also drop the export of mmc_vddrange_to_ocrmask(), but instead let's make it internal to the mmc core. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: of_mmc_spi: Convert to mmc_of_parse_voltage()Ulf Hansson1-21/+1
Let's drop the open-coding of the parsing of the "voltage-ranges" DT property and convert to use the common mmc_of_parse_voltage() API instead. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: core: Drop retries as in-parameter to mmc_wait_for_app_cmd()Ulf Hansson1-11/+5
All callers of mmc_wait_for_app_cmd() set the retries in-parameter to MMC_CMD_RETRIES. This is silly, so let's just drop the in-parameter altogether, as to simplify the code. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: core: Convert mmc_wait_for_app_cmd() to staticUlf Hansson2-19/+1
mmc_wait_for_app_cmd() is an internal function for sd_ops.c, thus let's drop the unnecessary export and turn it into static function. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: renesas_sdhi: Change HW adjustment register according to speed modeTakeshi Saito3-0/+11
SCC is used for SDR104/HS200/HS400. We need to change SCC_DT2FF according to the mode. If it is inappropriate, CRC error tends to occur. This adds variable "tap_hs400" for HS400 mode and configures SCC_DT2FF as needed. Signed-off-by: Takeshi Saito <takeshi.saito.xv@renesas.com> [wsa: rebased to upstream and updated commit message] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund@ragnatech.se> Tested-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: mmci: Send a CMD12 to clear the DPSM at errorsUlf Hansson2-2/+24
The current approach with sending a CMD12 (STOP_TRANSMISSION) to complete a data transfer request, either because of using the open-ended transmission type or because of receiving an error during a pre-defined data transfer, isn't sufficient for the STM32 sdmmc variant. More precisely, this variant needs to clear the DPSM ("Data Path State Machine") by sending a CMD12, for all failing ADTC commands. Support this, by adding a struct mmc_command inside the struct mmci_host and initialize it to a CMD12 during ->probe(). Let's also add checks for the new conditions, to enable mmci_data_irq() and mmci_cmd_irq() to postpone the calls to mmci_request_end(), but instead send the CMD12. Cc: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Barre <ludovic.barre@st.com>
2019-02-25mmc: sdhci-xenon: Fixup already marked switch fall-throughGustavo A. R. Silva1-1/+1
In preparation to enabling -Wimplicit-fallthrough, mark switch cases according to what the compiler looks for, where we are expecting to fall through. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci-tegra: drop ->get_ro() implementationThomas Petazzoni1-9/+0
The SDHCI core is know properly checking for the state of a WP GPIO, so there is no longer any need for the sdhci-tegra code to implement ->get_ro() using mmc_gpio_get_ro(). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci-omap: drop ->get_ro() implementationThomas Petazzoni1-1/+0
The SDHCI core is now properly checking for the state of a WP GPIO, so there is no longer any need for the sdhci-omap code to implement ->get_ro() using mmc_gpio_get_ro(). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci: use WP GPIO in sdhci_check_ro()Thomas Petazzoni1-0/+2
Even though SDHCI controllers may have a dedicated WP pin that can be queried using the SDHCI_PRESENT_STATE register, some platforms may chose to use a separate regular GPIO to route the WP signal. Such a GPIO is typically represented using the wp-gpios property in the Device Tree. Unfortunately, the current sdhci_check_ro() function does not make use of such GPIO when available: it either uses a host controller specific ->get_ro() operation, or uses the SDHCI_PRESENT_STATE. Several host controller specific ->get_ro() functions are implemented just to check a WP GPIO state. Instead of pushing this to more controller-specific implementations, let's handle this in the core SDHCI code, just like it is already done for the CD GPIO in sdhci_get_cd(). The below patch simply changes sdhci_check_ro() to use the value of the WP GPIO if available. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: wmt-sdmmc: Drop unused includeLinus Walleij1-1/+0
The WMT SDMMC driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> so drop this surplus include. Cc: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sunxi-mmc: Drop unused includesLinus Walleij1-2/+0
The Sunxi MMC driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these surplus includes. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Andre Przywara <andre.przywara@arm.com> Cc: cenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci-pxav2: Drop unused includeLinus Walleij1-1/+0
The SDHCI PXAv2 driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> so drop this surplus include. Cc: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci-bcm-kona: Drop unused includesLinus Walleij1-2/+0
The SDHCI BCM Kona driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these surplus includes. Cc: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: mxs-mmc: Drop unused includesLinus Walleij1-2/+0
The MXS-MMC driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these surplus includes. Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: mxcmmc: Drop unused includesLinus Walleij1-2/+0
The MXCMMC driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these surplus includes. Cc: Jun Qian <hangdianqj@163.com> Cc: Matteo Facchinetti <matteo.facchinetti@sirius-es.it> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: cb710: fix indentation issue in if blockColin Ian King1-20/+22
There is an if block that is not indented, fix this. Also add a break statement on the default case to clean up a cppcheck warning. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: core: Indicate SD specs higher than 4.0Avri Altman2-0/+7
SD specs version 4.x and 5.x have a dedicated slices in the SCR register. Higher versions will rely on a combination of the existing fields. Signed-off-by: Avri Altman <avri.altman@wdc.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: core: Calculate the discard arg only onceAvri Altman6-11/+21
In MMC, the discard arg is a read-only ext_csd parameter - set it once on card init. To be consistent, do that for SD as well even though its discard arg is always 0x0. Signed-off-by: Avri Altman <avri.altman@wdc.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: slot-gpio: Remove override_active_level on WPLinus Walleij9-16/+9
The argument "override_active_level" made it possible to enforce a specific polarity on the write-protect GPIO line. All callers in the kernel pass "false" to this call after I have converted all drivers to use GPIO machine descriptors, so remove the argument and clean out this. This kind of polarity inversion should be handled by the GPIO descriptor inside the GPIO library if needed. This rids us of one instance of the kludgy calls into the gpiod_get_raw_value() API. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: bcm2835: Deduplicate reset of driver data on removeLukas Wunner1-1/+0
The BCM2835 MMC host driver sets the device's driver data pointer to NULL on ->remove() even though the driver core subsequently does the same in __device_release_driver(). Drop the duplicate assignment. Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Lukas Wunner <lukas@wunner.de> Cc: Frank Pavlic <f.pavlic@kunbus.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: bcm2835: Drop pointer to mmc_host from bcm2835_hostLukas Wunner2-10/+15
The BCM2835 MMC host driver uses a pointer to get from the private bcm2835_host structure to the generic mmc_host structure. However the latter is always immediately preceding the former in memory, so compute its address with a subtraction (which is cheaper than a dereference) and drop the superfluous pointer. No functional change intended. Signed-off-by: Lukas Wunner <lukas@wunner.de> Cc: Frank Pavlic <f.pavlic@kunbus.de> Cc: Alexander Graf <agraf@suse.de> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: bcm2835: Drop DMA channel error pointer checkLukas Wunner1-1/+1
bcm2835_add_host() invokes IS_ERR_OR_NULL() on a DMA channel pointer, however dma_request_slave_channel() (which was used to populate the pointer) never returns an error pointer. So a NULL pointer check is sufficient. Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Lukas Wunner <lukas@wunner.de> Cc: Frank Pavlic <f.pavlic@kunbus.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: omap: fix the maximum timeout settingAaro Koskinen1-1/+1
When running OMAP1 kernel on QEMU, MMC access is annoyingly noisy: MMC: CTO of 0xff and 0xfe cannot be used! MMC: CTO of 0xff and 0xfe cannot be used! MMC: CTO of 0xff and 0xfe cannot be used! [ad inf.] Emulator warnings appear to be valid. The TI document SPRU680 [1] ("OMAP5910 Dual-Core Processor MultiMedia Card/Secure Data Memory Card (MMC/SD) Reference Guide") page 36 states that the maximum timeout is 253 cycles and "0xff and 0xfe cannot be used". Fix by using 0xfd as the maximum timeout. Tested using QEMU 2.5 (Siemens SX1 machine, OMAP310), and also checked on real hardware using Palm TE (OMAP310), Nokia 770 (OMAP1710) and Nokia N810 (OMAP2420) that MMC works as before. [1] http://www.ti.com/lit/ug/spru680/spru680.pdf Fixes: 730c9b7e6630f ("[MMC] Add OMAP MMC host driver") Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: tegra: HW Command Queue Support for Tegra SDMMCSowjanya Komatineni2-4/+114
This patch adds HW Command Queue for supported Tegra SDMMC controllers. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci: Add ADMA3 DMA support for V4 enabled hostSowjanya Komatineni2-1/+10
Below are the supported DMA types in Host Control1 Register with Version 4 enable b'00 - SDMA b'01 - Not Used b'10 - ADMA2 b'11 - ADMA2 or ADMA3 ADMA3 uses Command Descriptor to issue an SD command. A multi-block data transfer is performed by using a pair of CMD descriptor and ADMA2 descriptor. ADMA3 performs multiple of multi-block data transfer by using Integrated Descriptor which is more suitable for Command Queuing to fetch both Command and Transfer descriptors. Host Capabilities register indicates the supports of ADMA3 DMA. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25dt-bindings: mmc: Add supports-cqe propertySowjanya Komatineni1-0/+2
Add supports-cqe optional property for MMC hosts. This property is used to identify the specific host controller supporting command queue. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25MAINTAINERS: Drop link to git for SDHCIUlf Hansson1-1/+0
The git tree isn't used to maintain SDHCI, but instead we use the common MMC git tree. Let's drop it to avoid confusion. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
2019-02-25MAINTAINERS: Add maintainers for eMMC CQHCI driverUlf Hansson1-0/+8
The eMMC CQHCI is the host controller interface, introduced in the eMMC spec v5.1. The code was originally developed as collaboration among several people, however none really stepped in to maintain it. Let's add Adrian Hunter (Intel), Ritesh Harjani and Asutosh Das as the maintainers, whom knows both the code and the spec. Cc: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Ritesh Harjani <riteshh@codeaurora.org> Acked-by: Asutosh Das <asutoshd@codeaurora.org>
2019-02-25mmc: atmel-mci: enable 8 bits buswidth supportNicolas Ferre1-1/+7
This patch adds support for 8-bit buswidth. Relevant SDCR value modified. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: renesas_sdhi: Fix card initialization failure in high speed modeTakeshi Saito1-4/+7
This fixes card initialization failure in high speed mode. If U-Boot uses SDR or HS200/400 mode before starting Linux and Linux DT does not enable SDR/HS200/HS400 mode, card initialization fails in high speed mode. It is necessary to initialize SCC registers during card initialization phase. HW reset function is registered only for a port with either of SDR/HS200/HS400 properties in device tree. If SDR/HS200/HS400 properties are not present in device tree, SCC registers will not be reset. In SoC that support SCC registers, HW reset function should be registered regardless of the configuration of device tree. Reproduction procedure: - Use U-Boot that support MMC HS200/400 mode. - Delete HS200/HS400 properties in device tree. (Delete mmc-hs200-1_8v and mmc-hs400-1_8v) - MMC port works high speed mode and all commands fail. Signed-off-by: Takeshi Saito <takeshi.saito.xv@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Cc: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: jz4740: Remove platform data and use standard APIsPaul Cercueil1-57/+14
Drop the custom code to get the 'cd' and 'wp' GPIOs. The driver now calls mmc_of_parse() which will init these from devicetree or device properties. Also drop the custom code to get the 'power' GPIO. The MMC core provides us with the means to power the MMC card through an external regulator. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci: Remove unneeded quirk2 flag of O2 SD host controllerErnest Zhang(WH)1-1/+1
O2 SD host controller only need set the quirk2 flag SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD when work on force 1.8v emmc mode but not normal mode Signed-off-by: Ernest Zhang <ernest.zhang@bayhubtech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: jz4740: Annotate implicit fall throughMathieu Malaterre1-0/+2
There is a plan to build the kernel with -Wimplicit-fallthrough and these places in the code produced warnings (W=1). This commit removes the following warnings: drivers/mmc/host/jz4740_mmc.c:745:3: warning: this statement may fall through [-Wimplicit-fallthrough=] drivers/mmc/host/jz4740_mmc.c:779:3: warning: this statement may fall through [-Wimplicit-fallthrough=] Signed-off-by: Mathieu Malaterre <malat@debian.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci-esdhc-imx: fix return value check in sdhci_esdhc_imx_probe()Wei Yongjun1-2/+2
In case of error, the function devm_kzalloc() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: fadac7488064 ("mmc: sdhci-esdhc-imx: add CMDQ support") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: core: annotate implicit fall throughMathieu Malaterre1-1/+1
There is a plan to build the kernel with -Wimplicit-fallthrough and this place in the code produced a warning (W=1). In this particular case rewrote the comment to start with the string "fall through", so as to match the regular expression expected by GCC. Truncate the comment slightly to fit the max line length of 80 characters. This commit remove the following warning: drivers/mmc/core/host.c:196:14: warning: this statement may fall through [-Wimplicit-fallthrough=] Signed-off-by: Mathieu Malaterre <malat@debian.org> Acked-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: tegra: SDMMC pads auto-calibrationSowjanya Komatineni1-41/+119
Program initial drive code offsets which will be used by auto calibration process. Program fixed drive strengths for SDMMC pads in pad control register when auto cal timeouts. Fixed settings are based on Pre-SI analysis of the pad design. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25dt-bindings: mmc: tegra: Add pinctrl for SDMMC drive strengthsSowjanya Komatineni1-1/+5
Add pinctrls for 3V3 and 1V8 pad drive strength configuration for Tegra210 sdmmc. Tegra210 sdmmc has pad configuration registers in pinmux register domain and handled thru pinctrl to pinmux device node. Tegra186 and Tegra194 has pad configuration register with in the SDMMC register domain itself and are handles thru drive strength properties in sdmmc device node. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci-esdhc-imx: add DCMD support for CMDQBOUGH CHEN1-1/+21
Currently, USDHC do not generate transfer complete interrupt when send a non-data-command with R1b response. But if want to support DCMD in CMDQ, need to change this, the DCMD IC logic require the USDHC to enable this function, otherwise DCMD will never get a CC(command complete) interrupt. This patch set ESDHC_VEND_SPEC2_EN_BUSY_IRQ and add DCMD support. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci-esdhc-imx: add CMDQ supportBOUGH CHEN2-3/+115
Add CMDQ support for imx8qm/imx8qxp. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> [Ulf: Rebased on top of latest changes] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci: correct the maximum timeout when enable CMDQBOUGH CHEN1-2/+7
Change to use sdhci_set_timeout() to set the maximum timeout, so that the host can use it's own set_timeout() callback to set the maximum timeout if the host has. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci-esdhc-imx: add HS400_ES support for i.MX8QXPBOUGH CHEN1-0/+29
Add an new esdhc_soc_data for i.MX8QXP, and add HS400_ES mode support. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> [Ulf: Rebased on top of latest changes] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci-esdhc-imx: remove the 100MHz limitation for Strobe DLLBOUGH CHEN1-29/+23
For some eMMC, after switch to HS400ES mode, it need to config the strobe dll target dealy even if the clock is 50MHZ or 25MHz, otherwise will meet CMD index/crc error when send CMD13 to check the switch status. [ 2.473915] IRQ status 0x000a8001 [ 2.473934] mmc2: mmc_select_hs400es failed, error -84 [ 2.473938] mmc2: error -84 whilst initialising MMC card Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: tmio: undo PM autosuspend when removing the hostNiklas Söderlund1-0/+1
When removing the driver make sure to undo the PM autosuspend configured when probing the host. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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