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2020-05-18dt-bindings: clock: renesas: div6: Convert to json-schemaGeert Uytterhoeven2-40/+60
2020-05-18clk: renesas: cpg-mssr: Fix STBCR suspend/resume handlingGeert Uytterhoeven1-3/+5
2020-05-14Merge tag 'clk-meson-v5.8-1' of https://github.com/BayLibre/clk-meson into cl...Stephen Boyd5-62/+134
2020-05-14clk: ti: dra7xx: fix RNG clock parentTero Kristo1-1/+1
2020-05-14clk: ti: dra7xx: mark MCAN clock as DRA76x onlyTero Kristo1-1/+1
2020-05-14clk: ti: dra7xx: fix gpu clkctrl parentTero Kristo1-1/+1
2020-05-14clk: ti: omap5: Add proper parent clocks for l4-secure clocksTero Kristo1-7/+7
2020-05-14clk: ti: omap4: Add proper parent clocks for l4-secure clocksTero Kristo1-7/+7
2020-05-14clk: ti: composite: fix memory leakTero Kristo1-0/+1
2020-05-13clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542xMarek Szyprowski1-1/+1
2020-05-13clk: samsung: Mark top ISP and CAM clocks on Exynos542x as criticalMarek Szyprowski1-7/+9
2020-05-12clk: Move HAVE_CLK config out of architecture layerStephen Boyd2-6/+6
2020-05-12MIPS: Loongson64: Drop asm/clock.h includeStephen Boyd1-1/+0
2020-05-12ARM: mmp: Remove legacy clk codeStephen Boyd8-456/+0
2020-05-12clk: tegra: Add Tegra210 CSI TPG clock gateSowjanya Komatineni1-0/+7
2020-05-12clk: tegra30: Use custom CCLK implementationDmitry Osipenko1-2/+4
2020-05-12clk: tegra20: Use custom CCLK implementationDmitry Osipenko1-2/+5
2020-05-12clk: tegra: cclk: Add helpers for handling PLLX rate changesDmitry Osipenko2-0/+36
2020-05-12clk: tegra: pll: Add pre/post rate-change hooksDmitry Osipenko2-1/+17
2020-05-12clk: tegra: Add custom CCLK implementationDmitry Osipenko3-2/+188
2020-05-12clk: tegra: Remove the old emc_mux clock for Tegra210Joseph Lo1-19/+31
2020-05-12clk: tegra: Implement Tegra210 EMC clockJoseph Lo4-0/+397
2020-05-12clk: tegra: Export functions for EMC clock scalingJoseph Lo2-0/+29
2020-05-12clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210Joseph Lo2-2/+13
2020-05-12clk: tegra: Rename Tegra124 EMC clock source fileThierry Reding4-6/+2
2020-05-12Merge branch 'for-5.8/dt-bindings' into for-5.8/clkThierry Reding1-1/+1
2020-05-12dt-bindings: clock: tegra: Add clock ID for CSI TPG clockSowjanya Komatineni1-1/+1
2020-05-05clk: Allow the common clk framework to be selectableStephen Boyd9-9/+31
2020-05-05mmc: meson-mx-sdio: Depend on OF_ADDRESS and not just OFStephen Boyd1-1/+1
2020-05-05MIPS: Remove redundant CLKDEV_LOOKUP selectsStephen Boyd1-2/+0
2020-05-05h8300: Remove redundant CLKDEV_LOOKUP selectsStephen Boyd1-1/+0
2020-05-05arm64: tegra: Remove redundant CLKDEV_LOOKUP selectsStephen Boyd1-1/+0
2020-05-05ARM: Remove redundant CLKDEV_LOOKUP selectsStephen Boyd2-4/+0
2020-05-05ARM: Remove redundant COMMON_CLK selectsStephen Boyd3-3/+0
2020-05-05Merge tag 'clk-renesas-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/k...Stephen Boyd11-7/+367
2020-05-05clk: clk-xgene: Fix a typo in KconfigChristophe JAILLET1-1/+1
2020-05-05clk: Remove unused inline function clk_debug_reparentYueHaibing1-4/+0
2020-05-02clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl2-0/+13
2020-04-30clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selectsGeert Uytterhoeven1-3/+0
2020-04-30clk: renesas: cpg-mssr: Add R8A7742 supportLad Prabhakar5-0/+288
2020-04-29clk: meson: meson8b: Make the CCF use the glitch-free VPU muxMartin Blumenstingl1-3/+11
2020-04-29clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bitsMartin Blumenstingl1-5/+5
2020-04-29clk: meson: meson8b: Fix the polarity of the RESET_N linesMartin Blumenstingl1-23/+56
2020-04-29clk: meson: meson8b: Fix the first parent of vid_pll_in_selMartin Blumenstingl1-1/+1
2020-04-29dt-bindings: clocks: imx8mp: Add ids for audiomix clocksAbel Vesa1-0/+62
2020-04-29clk: imx: Add helpers for passing the device as argumentAbel Vesa1-0/+29
2020-04-29clk: imx: pll14xx: Add the device as argument when registeringAbel Vesa2-7/+14
2020-04-29clk: imx: gate2: Allow single bit gating clockAbel Vesa2-8/+36
2020-04-28Merge tag 'renesas-r8a7742-dt-binding-defs-tag' into clk-renesas-for-v5.8Geert Uytterhoeven2-0/+71
2020-04-28dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 bindingLad Prabhakar1-0/+1