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2018-08-27drm/scheduler: trivial error handling fixChristian König1-0/+3
Return -ENOMEM when allocating the rq_list fails. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu: fix integer overflow test in amdgpu_bo_list_create()Dan Carpenter1-1/+2
We accidentally left out the size of the amdgpu_bo_list struct. It could lead to memory corruption on 32 bit systems. You'd have to pick the absolute maximum and set "num_entries == 59652323" then size would wrap to 16 bytes. Fixes: 920990cb080a ("drm/amdgpu: allocate the bo_list array after the list") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Bas Nieuwenhuizen <basni@chromium.org> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/pp: OverDrive gfx domain voltage on TongaRex Zhu1-0/+1
Also ajust the gfx domain voltage on Tonga when user overdriver the voltage. For Tonga, Driver do not update user's setting to voltage table in smu, we only pick up a minimum value from voltage table that not less than the user's setting. v2: fix a typo Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu: Cancel the delay work when suspendRex Zhu1-0/+2
Cancel the delay work to avoid the corner case that ib test was not running when suspend Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu: remove experimental flag for vega20Alex Deucher1-6/+6
Now that PSP and SMU support is in place. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu/psp: Enlarge PSP TMR SIZE from 3M to 4M.Feifei Xu2-2/+5
Enlarge the PSP TMR SIZE to 4M for dual UVD fw front-door loading. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu: update vega20 sdma golden settingsEvan Quan1-11/+57
Updated vega20 SDMA0 and SDMA1 golden settings. Signed-off-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu/gfx9: Update gfx9 golden settings.Feifei Xu1-1/+1
Update the goldensettings for vega20. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: added voltage boot time calibrationEvan Quan1-0/+10
Run AFLL BTC after upload pptable and before enabling all smu features. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: remove max DCEFCLK limitationEvan Quan1-3/+0
The latest SMU fw removes the limitation that required UCLK >= DCEFCLK. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: allow slow switch only if NBPState enabledEvan Quan1-1/+2
Otherwise there may be potential SMU performance issues. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: correct the argument for PPSMC_MSG_SetUclkFastSwitchEvan Quan1-1/+1
The argument was set wrongly. Fast/slow switch was asked when there is actually a slow/fast switch needed. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: avoid enabling/disabling uvd/vce dpm twiceEvan Quan1-0/+6
For vega20, there are two UVD rings which share one powerplay instance. Under some case(two rings used parallel), the uvd dpm is disabled twice which causes the SMC hang. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: remove setting soc floor voltage before sending pptableEvan Quan2-9/+1
SOC voltage is not able to switch and forced to low 0.8V when running HEVC. Thus the test failed. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: enable fclk ss by defaultEvan Quan1-1/+1
Set fclk ss as enabled on default. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu/vg20: Change the load type of vega20 to psp (v2)Likun Gao1-2/+1
Modified the vega20 load type to psp now that psp support is implemented. v2: squash in fixes history (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu: Add psp 11.0 support for vega20. (v2)Feifei Xu7-6/+614
Add psp 11.0 code for vega20 and enable it. PSP is the security processor for the GPU. It handles firmware loading and GPU resets among other things. v2: whitespace fix, enable support, adjust reg includes (Alex) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu: enable vega20 powerplay supportEvan Quan1-2/+2
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: update vega20 clocks threshold settings on power state adjustEvan Quan1-0/+112
UVD, VCE and SOC clocks need to be taken into consideration. Also, the thresholds need be updated correspondingly when stable power state is selected. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: revise vega20 PPSMC_MSG_SetSoftMin/[Max]ByFreq settingsEvan Quan1-13/+96
UVD, VCE and Socclk also need to be taken into consideration when setting PPSMC_MSG_SetSoftMinByFreq and PPSMC_MSG_SetSoftMaxByFreq. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: new interfaces for overdrive vega20 sclk and mclkEvan Quan1-0/+169
Add support for the new SMU firmware interface for clock adjustment. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: initialize vega20 overdrive settingsEvan Quan5-49/+403
The initialized overdrive settings are taken from vbios and SMU( by PPSMC_MSG_TransferTableSmu2Dram). Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: conv the vega20 pstate sclk/mclk into necessary 10KHz unitEvan Quan1-0/+3
Powerplay uses 10KHz units. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: add vega20 pre_display_config_changed callbackEvan Quan1-0/+41
fix possible handshake hang and video playback crash Corner cases: - Handshake between SMU and DCE causes hangs when CRTC is not enabled - System crash occurs when starting 4K playback with Movies and TV in an SLS configuration Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: export vega20 stable pstate clocksEvan Quan1-1/+25
Needed for querying the stable pstate clocks. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: correct force clock level related settings for vega20 (v2)Evan Quan1-45/+64
1. The min/max level is determined by soft_min_level/soft_max_level. 2. Vega20 comes with pptable v3 which has no vdd related table(vdd_dep_on_socclk, vdd_dep_on_mclk) support. 3. Vega20 does not support separate fan feature control(enable or disable). v2: squash in fixes: - bug fix for force dpm level settings - fix wrong data type Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: init vega20 uvd/vce powergate status on dpm setupEvan Quan1-0/+18
This is essentially necessary when uvd/vce dpm is not enabled yet. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: support workload profile query and setup for vega20Evan Quan1-1/+192
Support the power profile API. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: add the hw manager for vega20 (v3)Evan Quan10-2/+3956
hwmgr is the interface for the driver to setup state structures which are used by the smu for managing the power state. v2: squash in fixes: - update set_watermarks_for_clocks_ranges to use common code - drop unsupported apis - correct MAX_REGULAR_DPM_NUMBER value - multimonitor fixes - add check for vbios pptable version - revise dpm table setup - init fclk dpm state - Remove unused definition in vega20_hwmgr - support power limit setup - enable vega20 to honour DAL clock limits - comment out dump_table debugging v3: switch to SOC15 register access macros Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: new interfaces for ActivityMonitor table with SMUEvan Quan2-0/+61
Vega20 has a new activity monitor table that is stored in memory. Add API to get and set the new table. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: add the smu manager for vega20 (v2)Evan Quan3-1/+592
The SMU manager handles the driver interaction with the SMU which handles clock and voltage controls. v2: switch to SOC15 register access macros reserve space for ActivityMonitor table enable SMU fw loading Drop dead code from bringup Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: add vega20_pptable.h (v2)Evan Quan1-0/+140
v2: squash in table size fixes Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: add vega20_ppsmc.h (v2)Evan Quan1-0/+127
v2: update to latest. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: add smu11_driver_if.h (v4)Evan Quan1-0/+831
v2: cleanup v3: fit the latest 40.6 smc fw v4: update to latest. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/powerplay: add vega20_inc.h (v2)Evan Quan1-0/+35
v2: use thm 11.0.2 headers Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu: update atomfirmware.hEvan Quan1-0/+86
Add struct atom_smc_dpm_info_v4_3 Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu: Add nbio 7.4 support for vega20 (v3)Feifei Xu5-1/+272
Some register offset in nbio v7.4 are different with v7.0. We need a seperate nbio_v7_4.c for vega20. v2: fix doorbell range for sdma (Alex) v3: squash in static fix (kbuild test robot) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27Revert "drm/amdgpu: Add nbio support for vega20 (v2)"Alex Deucher2-19/+1
Revert this to add proper nbio 7.4 support. This reverts commit f5b2e1fa321eff20a9418ebd497d8a466f024a85. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu/include: Add mp 11.0 header files. (v2)Feifei Xu2-0/+892
Add the system management controller v11.0 header files. v2: cleanup Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu/include: add thm 11.0.2 headersEvan Quan2-0/+123
Headers for thermal controller. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu/include: Add sdma0/1 4.2 register headerfiles. (v3)Feifei Xu4-0/+8026
These are the System DMA register headers for vega20. v2: cleanups (Alex) v3: add missing licenses (Alex) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu/include: Add nbio 7.4 header files (v4)Feifei Xu2-0/+53063
v2: Cleanups (Alex) v3: More updates (Alex) v4: more cleanups (Alex) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/radeon: enable ABGR and XBGR formats (v2)Mauro Rossi2-5/+51
Add support for DRM_FORMAT_{A,X}BGR8888 in atombios_crtc Swapping of red and blue channels is implemented for radeon chipsets: DCE2/R6xx and later - crossbar registers defined where needed and used DCE1/R5xx - AVIVO_D1GRPH_SWAP_RB bit is used (v2) Set AVIVO_D1GRPH_SWAP_RB bit in fb_format, using bitwise OR for DCE1 path Use bitwise OR where required for big endian settings in fb_swap Use existing code style CHIP_R600 condition, fix typo in R600 blue crossbar Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu: enable ABGR and XBGR formats (v2)Mauro Rossi6-0/+82
Add support for DRM_FORMAT_{A,X}BGR8888 in amdgpu with amd dc disabled (v2) Crossbar registers are defined and used to swap red and blue channels, keeping the existing coding style in each of the dce modules. After setting crossbar bits in fb_swap, use bitwise OR for big endian where required in DCE6 and DCE8 which do not rely on REG_SET_FIELD() Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: enable ABGR and XBGR formats (v4)Mauro Rossi1-0/+6
SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 is supported in amd/display/dc/dc_hw_types.h and the necessary crossbars register controls to swap red and blue channels are already implemented in drm/amd/display/dc/dce/dce_mem_input.c (v4) Logic to handle new formats is added only in amdgpu_dm module. Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu/powerplay/vega10: enable AVFS control via ppfeaturemaskAlex Deucher1-1/+2
Allow the user to disable AFVS via ppfeaturemask for debugging. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu/powerplay/smu7: enable AVFS control via ppfeaturemaskAlex Deucher1-1/+2
Allow the user to disable AFVS via ppfeaturemask for debugging. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu: add AVFS control to PP_FEATURE_MASKAlex Deucher1-0/+1
Add a ppfeaturemask flag to disable AVFS control. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: dc 3.1.62Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Steven Chiu <Steven.Chiu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Remove redundant non-zero and overflow checkLeo (Sunpeng) Li1-7/+3
[Why] Unsigned int is guaranteed to be >= 0, and read_channel_reply checks for overflows. read_channel_reply also returns -1 on error, which is what dc_link_aux_transfer is expected to return on error. [How] Remove the if-statement. Return result of read_channel_reply directly. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-17 15:39:37 +0000