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2015-04-02Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds5-1/+19
Pull dmaengine fixes from Vinod Koul: "This time we have addition of caps for jz4740 which fixes intentional warning at boot. Then we have memory leak issues in drivers using virt-dma by Peter on few drive" * 'fixes' of git://git.infradead.org/users/vkoul/slave-dma: dmaengine: moxart-dma: Fix memory leak when stopping a running transfer dmaengine: bcm2835-dma: Fix memory leak when stopping a running transfer dmaengine: omap-dma: Fix memory leak when terminating running transfer dmaengine: edma: fix memory leak when terminating running transfers dmaengine: jz4740: Define capabilities
2015-04-02Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netLinus Torvalds66-391/+758
Pull networking fixes from David Miller: 1) Fix use-after-free with mac80211 RX A-MPDU reorder timer, from Johannes Berg. 2) iwlwifi leaks memory every module load/unload cycles, fix from Larry Finger. 3) Need to use for_each_netdev_safe() in rtnl_group_changelink() otherwise we can crash, from WANG Cong. 4) mlx4 driver does register_netdev() too early in the probe sequence, from Ido Shamay. 5) Don't allow router discovery hop limit to decrease the interface's hop limit, from D.S. Ljungmark. 6) tx_packets and tx_bytes improperly accounted for certain classes of USB network devices, fix from Ben Hutchings. 7) ip{6}mr_rules_init() mistakenly use plain kfree to release the ipmr tables in the error path, they must instead use ip{6}mr_free_table(). Fix from WANG Cong. 8) cxgb4 doesn't properly quiesce all RX activity before unregistering the netdevice. Fix from Hariprasad Shenai. 9) Fix hash corruptions in ipvlan driver, from Jiri Benc. 10) nla_memcpy(), like a real memcpy, should fully initialize the destination buffer, even if the source attribute is smaller. Fix from Jiri Benc. 11) Fix wrong error code returned from iucv_sock_sendmsg(). We should use whatever sock_alloc_send_skb() put into 'err'. From Eugene Crosser. 12) Fix slab object leak on module unload in TIPC, from Ying Xue. 13) Need a READ_ONCE() when reading the cached RX socket route in tcp_v{4,6}_early_demux(). From Michal Kubecek. 14) Still too many problems with TPC support in the ath9k driver, so disable it for now. From Felix Fietkau. 15) When in AP mode the rtlwifi driver can leak DMA mappings, fix from Larry Finger. 16) Missing kzalloc() failure check in gs_usb CAN driver, from Colin Ian King. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (52 commits) cxgb4: Fix to dump devlog, even if FW is crashed cxgb4: Firmware macro changes for fw verison 1.13.32.0 bnx2x: Fix kdump when iommu=on bnx2x: Fix kdump on 4-port device mac80211: fix RX A-MPDU session reorder timer deletion MAINTAINERS: Update Intel Wired Ethernet Driver info tipc: fix a slab object leak net/usb/r8152: add device id for Lenovo TP USB 3.0 Ethernet af_iucv: fix AF_IUCV sendmsg() errno openvswitch: Return vport module ref before destruction netlink: pad nla_memcpy dest buffer with zeroes bonding: Bonding Overriding Configuration logic restored. ipvlan: fix check for IP addresses in control path ipvlan: do not use rcu operations for address list ipvlan: protect against concurrent link removal ipvlan: fix addr hash list corruption net: fec: setup right value for mdio hold time net: tcp6: fix double call of tcp_v6_fill_cb() cxgb4vf: Fix sparse warnings netns: don't clear nsid too early on removal ...
2015-04-02drm/panel: Add support for Ampire AM-800480R3TMQW-A1H 800x480 7" panelPhilipp Zabel2-0/+35
This adds support for the AM-800480R3TMQW-A1H 7" 800x480 panel to the DRM simple panel driver. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02of: Add vendor prefix for Ampire Co., Ltd.Philipp Zabel1-0/+1
Add Ampire Co., Ltd. to the list of device tree vendor prefixes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: Add display timing for HannStar HSD070PWW1Philipp Zabel1-13/+13
The HannStar HSD070PWW1 LVDS panel data sheet lists allowed ranges additionally to the typical values for pixel clock rate (64.3-82 MHz) and blanking intervals (54-681 clock cycles horizontally, 3-23 lines vertically). This patch replaces this panel's display mode with the display timing information to describe acceptable timings. Since the HSYNC and VSYNC are unused, the distribution between front porches, back porches, and sync pulse lengths was chosen at will. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: simple: Add display timing supportPhilipp Zabel2-0/+43
The simple panel driver's ->get_modes() implementation calculates the display mode list from the typical timings and the ->get_timings() implementation returns the timings to the connected encoder for mode validation and fixup. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> [treding@nvidia.com: select VIDEOMODE_HELPERS] Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: Add display timing supportPhilipp Zabel1-0/+5
Many panel data sheets, additionally to typical values, list allowed ranges for timings such as hsync/vsync lengths, porches, and the pixel clock rate. These can be stored in a struct display_timing, to be used by an encoder mode_fixup callback to clamp user provided timing values or to validate workarounds for clock source limitations. This patch adds a new drm_panel_funcs callback that returns the panel's available display_timing entries. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: Add support for OrtusTech COM43H4M85ULC panelPhilipp Zabel2-0/+34
This adds support for the COM43H4M85ULC 3.7" 800x480 panel to the DRM simple panel driver. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02of: Add vendor prefix for Ortus Technology Co., Ltd.Philipp Zabel1-0/+1
Add Ortus Technology Co., Ltd. to the list of device tree vendor prefixes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: Add bus format for Giantplus GPG482739QS5 panelPhilipp Zabel1-0/+1
This patch adds the bus_format field to the GPG482739QS5 panel structure. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: simple: Add support for AUO b101ean01 panelHuang Lin2-0/+33
The AUO b101ean01 panel is a 10.1" 1280x800 panel which can be supported by the simple panel driver. Signed-off-by: Huang Lin <hl@rock-chips.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: simple: Add support for Innolux ZJ070NA-01PMichael Grzeschik2-0/+33
The Innolux ZJ070NA-01P is a 7.0" TFT LCD panel with an integrated LED backlight unit. This panel is used on the Technexion Toucan. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: simple: Add support for Innolux AT043TN24Nicolas Ferre2-0/+35
The Innolux AT043TN24 4.3" WQVGA TFT LCD panel. This panel with backlight is found in PDA 4.3" LCD screen (TM43xx series for instance). Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: simple: Add support for Shelly SCA07010-BFN-LNNBoris BREZILLON2-0/+33
The Shelly SCA07010-BFN-LNN is a 7.0" WVGA TFT LCD panel. This panel with backlight is found in PDA 7" LCD screen (TM70xx series for instance). Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/panel: simple: Add support for Samsung LTN140AT29 panelStéphane Marchesin2-0/+33
This panel is used by the Nyan Blaze board and can be supported by the simple-panel driver. Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> [tomeu.vizoso@collabora.com: add device tree binding document] Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02IB/uverbs: Prevent integer overflow in ib_umem_get address arithmeticShachar Raindel1-0/+8
Properly verify that the resulting page aligned end address is larger than both the start address and the length of the memory area requested. Both the start and length arguments for ib_umem_get are controlled by the user. A misbehaving user can provide values which will cause an integer overflow when calculating the page aligned end address. This overflow can cause also miscalculation of the number of pages mapped, and additional logic issues. Addresses: CVE-2014-8159 Cc: <stable@vger.kernel.org> Signed-off-by: Shachar Raindel <raindel@mellanox.com> Signed-off-by: Jack Morgenstein <jackm@mellanox.com> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
2015-04-02drm/tegra: sor: Reset during initializationTomeu Vizoso1-0/+18
As there isn't a way for the firmware on the Nyan Chromebooks to hand over the display to the kernel, and the kernel isn't redoing the whole configuration at present. With this patch, the SOR is brought to a known state and we get correct display on every boot. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: gem: Return 64-bit offset for mmap(2)Sean Paul1-1/+2
On 64-bit targets, tegra_gem_mmap() only returns a partial offset to userspace. As such, subsequent calls to mmap(2) may fail. Change the arguments to use a 64-bit offset to fix this. Signed-off-by: Sean Paul <seanpaul@chromium.org> Acked-by: Erik Faye-Lund <kusmabite@gmail.com> [treding@nvidia.com: tweak commit message] Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: hdmi: Name register fields consistentlyThierry Reding2-2/+2
Name the fields of the SOR_SEQ_CTL register consistently. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: hdmi: Resets are synchronousThierry Reding1-1/+1
Resets on Tegra are synchronous, so keep the clock enabled while asserting the reset. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: dc: Document tegra_dc_state_setup_clock()Thierry Reding1-0/+12
This function is called by output drivers so should be documented. While at it, move it to a more appropriate location. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: dc: Remove unused callbacksThierry Reding1-2/+0
The ->mode_set() and ->mode_set_base() callbacks are no longer used with full atomic mode-setting drivers, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: dc: Remove unused functionThierry Reding2-22/+0
The tegra_dc_setup_clock() function is unused after the conversion to atomic mode-setting, so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: dc: Use base atomic state helpersThierry Reding1-13/+18
Instead of duplicating the code, make use of the newly introduced atomic state duplicate and destroy helpers. This allows changes to the base atomic state handling to automatically propagate to the Tegra driver and thereby prevent breakage resulting from both copies going out of sync. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/atomic: Add helpers for state-subclassing driversThierry Reding2-16/+142
Drivers that subclass CRTC, plane or connector state need to carefully duplicate the code that the atomic helpers have. This is bound to cause breakage eventually because it requires auditing all drivers and update them when code is added to the helpers. In order to avoid that, implement new helpers that perform the required steps when copying and destroying state. These new helpers are exported so that state-subclassing drivers can use them. The default helpers are implemented using them as well, providing a single location that needs to be changed when adding to base atomic states. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: dc: Implement hardware VBLANK counterThierry Reding4-13/+35
The display controller on Tegra can use syncpoints to count VBLANK events. syncpoints are 32-bit unsigned integers, so well suited as VBLANK counters. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02gpu: host1x: Export host1x_syncpt_read()Thierry Reding2-0/+7
This function is used to read the current value of the syncpt and is useful in situations where drivers don't schedule work and wait for the syncpoint to increment. One particular use-case is using the syncpoint as a VBLANK counter. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: sor: Dump registers via debugfsThierry Reding1-6/+165
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: sor: Registers are 32-bitThierry Reding1-7/+6
Use a sized unsigned 32-bit data type (u32) to store register contents. The SOR registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: Provide debugfs file for the IOVA spaceThierry Reding1-0/+10
The Tegra DRM driver uses a single IO virtual address space for buffer mappings. Provide a table of the address space usage in debugfs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: dc: Check for valid parent clockThierry Reding1-0/+3
Check that the desired parent clock is indeed a valid parent for the display controller clock. This is purely cosmetic at this point since the parent clocks are specified in DT and all the currently defined parents are in fact valid parents of the display controller clock. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02perf/x86/intel: Fix Haswell CYCLE_ACTIVITY.* counter constraintsAndi Kleen1-3/+3
Some of the CYCLE_ACTIVITY.* events can only be scheduled on counter 2. Due to a typo Haswell matched those with INTEL_EVENT_CONSTRAINT, which lead to the events never matching as the comparison does not expect anything in the umask too. Fix the typo. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: http://lkml.kernel.org/r/1425925222-32361-1-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-04-02perf/x86/intel: Filter branches for PEBS eventKan Liang1-2/+2
For supporting Intel LBR branches filtering, Intel LBR sharing logic mechanism is introduced from commit b36817e88630 ("perf/x86: Add Intel LBR sharing logic"). It modifies __intel_shared_reg_get_constraints() to config lbr_sel, which is finally used to set LBR_SELECT. However, the intel_shared_regs_constraints() function is called after intel_pebs_constraints(). The PEBS event will return immediately after intel_pebs_constraints(). So it's impossible to filter branches for PEBS events. This patch moves intel_shared_regs_constraints() ahead of intel_pebs_constraints(). We can safely do that because the intel_shared_regs_constraints() function only returns empty constraint if its rejecting the event, otherwise it returns NULL such that we continue calling intel_pebs_constraints() and x86_get_event_constraint(). Signed-off-by: Kan Liang <kan.liang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1427467105-9260-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-04-02drm/radeon: fix wait in radeon_mn_invalidate_range_startChristian König1-7/+4
We need to wait for all fences, not just the exclusive one. Signed-off-by: Christian König <christian.koenig@amd.com> Cc: <stable@vger.kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-04-02drm/radeon: add extra check in radeon_ttm_tt_unpin_userptrChristian König1-0/+4
We somehow try to free the SG table twice. Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=89734 Signed-off-by: Christian König <christian.koenig@amd.com> Cc: <stable@vger.kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-04-02drm: Exynos: Respect framebuffer pitch for FIMD/MixerDaniel Stone2-10/+15
When performing a modeset, use the framebuffer pitch value to set FIMD IMG_SIZE and Mixer SPAN registers. These are both defined as pitch - the distance between contiguous lines (bytes for FIMD, pixels for mixer). Fixes display on Snow (1366x768). Signed-off-by: Daniel Stone <daniels@collabora.com> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-04-02kgdb/x86: Fix reporting of 'si' in kgdb on x86_64Steffen Liebergeld1-1/+1
This patch fixes an error in kgdb for x86_64 which would report the value of dx when asked to give the value of si. Signed-off-by: Steffen Liebergeld <steffen.liebergeld@kernkonzept.com> Cc: Jason Wessel <jason.wessel@windriver.com> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-04-02x86/asm/entry/64: Disable opportunistic SYSRET if regs->flags has TF setAndy Lutomirski1-1/+15
When I wrote the opportunistic SYSRET code, I missed an important difference between SYSRET and IRET. Both instructions are capable of setting EFLAGS.TF, but they behave differently when doing so: - IRET will not issue a #DB trap after execution when it sets TF. This is critical -- otherwise you'd never be able to make forward progress when returning to userspace. - SYSRET, on the other hand, will trap with #DB immediately after returning to CPL3, and the next instruction will never execute. This breaks anything that opportunistically SYSRETs to a user context with TF set. For example, running this code with TF set and a SIGTRAP handler loaded never gets past 'post_nop': extern unsigned char post_nop[]; asm volatile ("pushfq\n\t" "popq %%r11\n\t" "nop\n\t" "post_nop:" : : "c" (post_nop) : "r11"); In my defense, I can't find this documented in the AMD or Intel manual. Fix it by using IRET to restore TF. Signed-off-by: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Borislav Petkov <bp@suse.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Fixes: 2a23c6b8a9c4 ("x86_64, entry: Use sysret to return to userspace when possible") Link: http://lkml.kernel.org/r/9472f1ca4c19a38ecda45bba9c91b7168135fcfa.1427923514.git.luto@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-04-02drm/i915: Reject the colorkey ioctls for primary and cursor planesVille Syrjälä1-2/+2
The legcy colorkey ioctls are only implemented for sprite planes, so reject the ioctl for primary/cursor planes. If we want to support colorkeying with these planes (assuming we have hw support of course) we should just move ahead with the colorkey property conversion. Testcase: kms_legacy_colorkey Cc: Tommi Rantala <tt.rantala@gmail.com> Cc: stable@vger.kernel.org Reference: http://mid.gmane.org/CA+ydwtr+bCo7LJ44JFmUkVRx144UDFgOS+aJTfK6KHtvBDVuAw@mail.gmail.com Reported-and-tested-by: Tommi Rantala <tt.rantala@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-04-01drm/msm/mdp5: Enable DSI connector in msm drm driverHai Li8-7/+497
This change adds the support in mdp5 kms driver for single and dual DSI. Dual DSI case depends on the framework API and sequence change to support dual data path. v1: Initial change v2: Address Rob Clark's comment - Separate command mode encoder to a new file mdp5_cmd_encoder.c - Rebase to not depend on msm_drm_sub_dev change Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm: Initial add DSI connector supportHai Li8-0/+3423
This change adds the DSI connector support in msm drm driver. v1: Initial change v2: - Address comments from Archit + minor clean-ups - Rebase to not depend on msm_drm_sub_dev change [Rob's comment] v3: Fix issues when initialization is failed Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm: Add split display interfaceHai Li1-0/+4
This change is to add an interface to MDP for connector devices setting split display information. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Move *_modeset_init out of construct_encoder functionHai Li1-35/+54
This change is to make the content in construct_encoder reflect its name. Also, DSI connector may be connected to video mode or command mode encoder, so that 2 different encoders need to be constructed for DSI. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm: export tile-group functionsRob Clark1-0/+2
Normally these are called from within drm core, from the EDID parsing code. But for dual-dsi in some drivers (at least drm/msm) we need to call these from the driver. So they should be exported. Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: Dave Airlie <airlied@redhat.com>
2015-04-01drm/msm/mdp5: Remove CTL flush dummy bitsStephane Viau1-11/+0
This TODO can now be removed and replaced by the previous patch "drm/msm/mdp5: Update headers (add CTL flush bits)" Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update headers (add CTL flush bits)Stephane Viau1-2/+10
Some upcoming targets have more bits to set in CTL_FLUSH registers. Example: msm8x16 needs to set TIMING1 bit so that some of the INTF1's interface registers get flushed. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Add hardware configuration for msm8x16Stephane Viau1-1/+51
This change adds the hw configuration for msm8x16 chipsets in mdp5_cfg module. Note that only one external display interface is present in this configuration (DSI) but has not been enabled yet. It will be enabled once drm/msm driver supports DSI connectors. v2: add CTL flush register's hardware mask [pointed by Archit] Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Get SMP client list from mdp5_cfgStephane Viau3-24/+41
SMP blocks are configured for specific client IDs (ports). These client IDs can be different from one chip to another for a given pipe. e.g.: DMA0 pipe fetch Y component is connected to: - port #10 for MDP5 v1.3 - port #4 for MDP5 v1.6 In order to be compatible for upcoming versions of MDP5, the client ID list is passed through the MDP5 config module rather than using a list of hard-coded enum values. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update headers (remove enum mdp5_client_id)Stephane Viau1-34/+7
This patch contains the generated header file of the following change "drm/msm/mdp5: Get SMP client list from mdp5_cfg". Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Separate MDP5 domain from MDSS domainStephane Viau7-38/+48
MDP block is actually contained inside the MDSS block. For some chipsets, the base address of the MDP registers is different from the current (assumed) 0x100 offset. Like CTL and LM blocks, this changes introduce a dynamic offset for the MDP instance, which can be found out at runtime, once the MDSS HW version is read. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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