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2022-11-09drm/nouveau/gsp: add funcsBen Skeggs5-7/+20
Ampere. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo/ga100-: initial supportBen Skeggs13-276/+610
- replaces the hacked-up version that existed solely to support TTM v2. remove earlier hack preventing use of non-stall intr for fences Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2022-11-09drm/nouveau/ce/ga100-: initial supportBen Skeggs8-0/+144
- replaces the hacked-up version that existed solely to support TTM - noop until the next commit, adding proper support for ampere host v2. fixup for ga103 early merge Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2022-11-09drm/nouveau/fifo: add new channel classesBen Skeggs63-1763/+524
Exposes a bunch of the new features that became possible as a result of the earlier commits. DRM will build on this in the future to add support for features such as SCG ("async compute") and multi-device rendering, as part of the work necessary to be able to write a half- decent vulkan driver - finally. For the moment, this just crudely ports DRM to the API changes. - channel class interfaces now the same for all HW classes - channel group class exposed (SCG) - channel runqueue selector exposed (SCG) - channel sub-device id control exposed (multi-device rendering) - channel names in logging will reflect creating process, not fd owner - explicit USERD allocation required by VOLTA_CHANNEL_GPFIFO_A and newer - drm is smarter about determining the appropriate channel class to use Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add new engine object handlingBen Skeggs22-228/+94
Simplifies the GPU-specific code, completing the switch to newer HALs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add new engine context handlingBen Skeggs39-930/+382
Builds on the context tracking that was added earlier. - marks engine context PTEs as 'priv' where possible Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add RAMFC info to nvkm_chan_funcBen Skeggs29-321/+488
- adds support for specifying SUBDEVICE_ID for channel - rounds non-power-of-two GPFIFO sizes down, rather than up Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add USERD info to nvkm_chan_funcBen Skeggs23-115/+157
And use it to cleanup multiple implementations of almost the same thing. - prepares for non-polled / client-provided USERD - only zeroes relevant "registers", rather than entire USERD Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add RAMIN info to nvkm_chan_funcBen Skeggs16-20/+64
Currently provided by {chan,dma,gpfifo}*.c, and those are going away. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add common runlist controlBen Skeggs35-505/+284
- less dependence on waiting for runlist updates, on GPUs that allow it - supports runqueue selector in RAMRL entries - completes switch to common runl/cgrp/chan topology info Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add common channel recoveryBen Skeggs19-605/+559
That sure was fun to untangle. - handled per-runlist, rather than globally - more straight-forward process in general - various potential SW/HW races have been fixed - fixes lockdep issues that were present in >=gk104's prior implementation - volta recovery now actually stands a chance of working - volta/turing waiting for PBDMA idle before engine reset - turing using hw-provided TSG info for CTXSW_TIMEOUT Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: kill channel on NV_PPBDMA_INTR_1_CTXNOTVALIDBen Skeggs3-0/+30
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: kill channel on a selection of PBDMA errorsBen Skeggs1-3/+3
A bunch of these can be handled in such a way that the channel can continue, however, any of these are a pretty decent sign something has gone horribly wrong, and the safest option is to disable the channel. This is a bit of a hack, we will want to handle these individually and dump relevant debug info for each at some point. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add chan/cgrp preempt()Ben Skeggs19-86/+102
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add chan start()/stop()Ben Skeggs27-108/+191
- nvkm_chan_error() built on top, stops channel and sends 'killed' event - removes an odd double-bashing of channel enable regs on kepler and up - pokes doorbell on turing and up, after enabling channel Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add chan bind()/unbind()Ben Skeggs17-37/+115
- stops programming (non-existent) runl id field on bind(), from maxwell Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add runlist block()/allow()Ben Skeggs13-14/+95
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add runlist wait()Ben Skeggs15-32/+102
- adds g8x/turing registers, which were missing before - switches fermi to polled wait, like later hw (see: 4f2fc25c0f8bc...) Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add new engine context trackingBen Skeggs7-10/+296
Channel groups have somewhat more complicated requirements than what we currently support. An engine context is shared between all channels in a channel group, VEID/subctx support (later) brings per-VEID components, and we need to track an individual channel's engine context pointers. This commit adds the structures and refcounting to support the above, wrapping the prior implementation for the moment. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add new channel lookup interfacesBen Skeggs28-132/+166
- supports per-runlist CHIDs - channel group lock held across reference, rather than global lock v2: - remove unnecessary parenthesis Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: merge mmu fault handlers togetherBen Skeggs14-335/+183
After updating GF100 implementation from the GK104/TU102 ones, and using the new runlist/engine topology info, all three handlers become (almost) identical. - there's a temporary kludge to call through to the HW-specific recovery - engine fault mapping info determined at load time, not on every fault Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: move PBDMA intr to runqBen Skeggs8-102/+84
- merges gf100/gk104- NV_PFIFO_INTR_0_PBDMA and NV_PPBDMA_INTR_0 code Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: move PBDMA init to runqBen Skeggs15-74/+36
- bumps pbdma timeout to value RM uses on newer HW - bumps fb timeout to max from boot default - one/both of these greatly improves stability on // piglit runs Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: program NV_PFIFO_FB_TIMEOUT on initBen Skeggs2-0/+2
NVGPU and RM both program this value. Fixes a bunch of random hangs running parallel piglit. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2022-11-09drm/nouveau/fifo: tidy global PBDMA initBen Skeggs14-32/+52
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2022-11-09drm/nouveau/fifo: tidy up non-stall intr handlingBen Skeggs20-118/+93
- removes a layer of indirection in the intr handling - prevents non-stall ctrl racing with unknown intrs Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: use explicit intr interfacesBen Skeggs17-89/+105
More control, and shallower call-chain to get to the point. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: use runlist engine info to lookup engine classesBen Skeggs22-146/+35
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add cgrp, have all channels be part of oneBen Skeggs13-18/+231
Engine context tracking will move to nvkm_cgrp in later commits, so we create SW-only channel groups on HW without support for them. - switches to nvkm_chid for TSG/channel ID allocation Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: expose per-runlist CHID informationBen Skeggs8-21/+80
DRM uses this to setup fence-related items. - nouveau_chan.runlist will always be "0" for the moment, not an issue as GPUs prior to ampere have system-wide channel IDs, Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: expose runlist topology info on all chipsetsBen Skeggs17-116/+81
Previously only available from Kepler onwards. - also fixes the info() queries causing fifo init()/fini() unnecessarily Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add common runlist/engine topologyBen Skeggs26-43/+583
Creates an nvkm_runl for each runlist on the GPU, and an nvkm_engn for each engine that is reachable from a runlist. - basically what gk104- already does, but extended to all chips - adds per-runlist CHID allocators (Ampere) - splits g98/gt2xx out from g84 (different target engines) Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add runqBen Skeggs17-27/+153
Creates an nvkm_runq for each PBDMA, these will be associated with the relevant runlist(s) later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add chid allocatorBen Skeggs26-21/+209
We need to be able to allocate TSG IDs as well as channel IDs, also, Ampere has per-runlist channel IDs. - holds per-ID private data, which will be used for/to protect lookup - holds an nvkm_event which will be used for events tied to IDs - not used yet beyond setup, and switching use of "fifo->nr - 1" for channel ID mask to "chid->mask" Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: merge gk104_fifo_func into nvkm_host_funcBen Skeggs14-111/+219
This makes it easier to transition everything. - a couple of function renames for collisions Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: pre-move some blocks of code aroundBen Skeggs6-400/+400
- will make subsequent patches more obvious - no code changes Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: unify handling of channel classesBen Skeggs36-191/+410
Adds the basic skeleton for common channel (group) interfaces. - common behaviour between <gk104 and >=gk104 impl's - separates priv/user channel objects - passthrough to existing object for now, kludges removed later Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fifo: add chid_nr()Ben Skeggs25-137/+114
- reads channel count from GPU from gm200 onwards - removes gm20b/gp10b (they become identical to gm200/gp100) Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/imem: allow bar2 mapping of user allocationsBen Skeggs6-6/+46
Will be used to init client-allocated USERD to default values. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/flcn: show falcon user in debug outputBen Skeggs3-16/+22
Displays both owner/user of the falcon (when they differ), and takes both subdevs' debug levels into account when deciding whether to log the message. - runlist debugging will use one of the alternate macros added here Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/nvkm: add locking to subdev/engine init pathsBen Skeggs4-69/+142
This wasn't really needed before; the main place this could race is with channel recovery, but (through potentially fragile means) shouldn't have been possible. However, a number of upcoming patches benefit from having better control over subdev init, necessitating some improvements here. - allows subdev/engine oneinit() without init() (host/fifo patches) - merges engine use locking/tracking into subdev, and extends it to fix some issues that will arise with future usage patterns (acr patches) Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/mc/ga100: switch to using NV_PMC_DEVICE_ENABLEBen Skeggs1-3/+44
- NV_PMC_ENABLE still exists, but we don't touch anything in it yet Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/mc: move NV_PMC_ENABLE bashing to chipset-specific codeBen Skeggs16-11/+56
Ampere needs different handling here, most of what we touch has moved. We probably want to refactor these interfaces in general, but I'm not yet sure how they should look, this will get the job done for now. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/mc: implement intr handling on top of nvkm_intrBen Skeggs21-577/+285
- new-style handlers can now be used here too - decent clean-up Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/fault/ga100: initial supportBen Skeggs1-0/+6
TU102 implementation should be OK for Ampere now. v2. fixup for ga103 early merge Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2022-11-09drm/nouveau/fault/tu102: switch to explicit intr handlersBen Skeggs4-72/+52
- reads vectors from HW, rather than being hardcoded - removes hacks to support routing via old interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/vfn/tu102-: support new-style interrupt treeBen Skeggs6-15/+99
- switches ampere over now, and removes its hack mc implementation Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/vfn: move NV_USERMODE class from hostBen Skeggs17-92/+67
- uses proper class IDs for Turing/Ampere Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/vfn: add stub subdev for dev_funcBen Skeggs11-0/+197
Initially for NV_USERMODE class, and Turing/Ampere's new interrupt tree. v2. fixup for ga103 early merge Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2022-11-09drm/nouveau/intr: add nvkm_subdev_intr() compatibilityBen Skeggs4-0/+65
It's quite a lot of tedious and error-prone work to switch over all the subdevs at once, so allow an nvkm_intr to request new-style handlers to be created that wrap the existing interfaces. This will allow a more gradual transition. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-12 23:34:57 +0000