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2017-01-03OF: Prevent unaligned access in of_alias_scan()Paul Burton1-1/+1
When allocating a struct alias_prop, of_alias_scan() only requested that it be aligned on a 4 byte boundary. The struct contains pointers which leads to us attempting 64 bit writes on 64 bit systems, and if the CPU doesn't support unaligned memory accesses then this causes problems - for example on some MIPS64r2 CPUs including the "mips64r2-generic" QEMU emulated CPU it will trigger an address error exception. Fix this by requesting alignment for the struct alias_prop allocation matching that which the compiler expects, using the __alignof__ keyword. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Cc: Frank Rowand <frowand.list@gmail.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14306/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: IRQ: Remove useless i8259_of_init() prototype.Ralf Baechle1-1/+0
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: uprobes: Remove __weak attribute from arch_uprobe_copy_ixol.Marcin Nowakowski1-1/+1
Arch-specific implementation of arch_uprobe_copy_ixol is expected to override the weak implementation in generic code. As currently both implementations are marked as weak, it is up to the linker to chose one. Remove the __weak attribute from MIPS code to make sure the correct version is used. Fixes: 40e084a506eb ("MIPS: Add uprobes support.") Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14660/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: ralink: Cosmetic change to prom_init().John Crispin1-5/+4
Over the years the code has been changed various times leading to argc/argv being defined in a different function to where we actually use the variables. Clean this up by moving them to prom_init_cmdline(). Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14902/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: ralink: Add missing symbol for highmem support.John Crispin1-0/+1
MT7621 has highmem. this was previously not working as the required symbol was not selected in the Kconfig file. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14901/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: ralink: Add missing clk_round_rate().John Crispin1-0/+6
As we dont use the common clock api yet we need to add this stub to allow building drivers that use the API. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14900/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: ralink: Fix a typo in the pinmux setup.John Crispin1-9/+9
There is a typo inside the pinmux setup code. The function is really called utif and not util. This was recently discovered when people were trying to make the UTIF interface work. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14899/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: ralink: Add missing pinmux.John Crispin2-3/+12
The mt7620 has a pin that can be used to generate an external reference clock. The pinmux setup was missing the definition of said pin. This patch adds it. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14898/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: ralink: Add missing I2C and I2S clocks.John Crispin4-0/+10
This patch adds two additional clocks required by the audio interface of the SoCs. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14897/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: ralink: MT7621 does not set its SoC type.John Crispin1-1/+1
The code does not set the SoC type properly. This went unnoticed until now as the SoC does not share any of the driver code with the other SoCs, until we made the mmc driver work. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14896/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Add cacheinfo supportJustin Chen2-1/+86
Add cacheinfo support for MIPS architectures. Use information from the cpuinfo_mips struct to populate the cacheinfo struct. This allows an architecture agnostic approach, however this also means if cache information is not properly populated within the cpuinfo_mips struct, there is nothing we can do. (I.E. c-r3k.c) Signed-off-by: Justin Chen <justin.chen@broadcom.com> Cc: f.fainelli@gmail.com Cc: linux-mips@linux-mips.org Cc: bcm-kernel-feedback-list@broadcom.com Patchwork: https://patchwork.linux-mips.org/patch/14650/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: generic/kexec: add support for a DTB passed in a separate bufferMarcin Nowakowski2-0/+45
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14615/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: kexec: add debug info about the new kexec'ed imageMarcin Nowakowski1-0/+22
Print details of the new kexec image loaded. Based on the original code from commit 221f2c770e10d ("arm64/kexec: Add pr_debug output") Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14614/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: kexec: Do not reserve invalid crashkernel memory on bootMarcin Nowakowski1-0/+5
Do not reserve memory for the crashkernel if the commandline argument points to a wrong location. This can happen if the location is specified wrong or if the same commandline is reused when starting the crashkernel - in the latter case the reserved memory would point to the location from which the crashkernel is executing. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14612/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: fix mem=X@Y commandline processingMarcin Nowakowski1-0/+4
When a memory offset is specified through the commandline, add the memory in range PHYS_OFFSET:Y as reserved memory area. Otherwise the bootmem allocator is initialised with low page equal to min_low_pfn = PHYS_OFFSET, and in free_all_bootmem will process pages starting from min_low_pfn instead of PFN(Y). Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14613/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: relocate: Optionally relocate the DTBMarcin Nowakowski1-2/+36
If the DTB is located in the target memory area for the relocated kernel it needs to be relocated as well before kernel relocation takes place. After copying the DTB use the new plat_fdt_relocated() API from the relocated kernel to ensure the relocated kernel updates any information that it may have cached about the location of the DTB. plat_fdt_relocated is declared as a weak symbol so that platforms that do not require it do not need to implement the method. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14616/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: platform: Allow for DTB to be moved during kernel relocationMarcin Nowakowski2-0/+26
Add plat_fdt_relocated(void*) API to allow the kernel relocation code to update platform's information about the DTB location if the DTB had to be moved due to being placed in a location used by the relocated kernel. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14611/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Use early_init_fdt_reserve_self to protect DTB locationMarcin Nowakowski2-0/+11
early_init_fdt_reserve_self is used to tell the boot memory allocator that a memory is occupied by the DTB, so add it in the MIPS init code to ensure information about the DTB is added to the boot memory array. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14610/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: init: Ensure bootmem does not corrupt reserved memoryMarcin Nowakowski1-3/+71
Current init code initialises bootmem allocator with all of the low memory that it assumes is available, but does not check for reserved memory block, which can lead to corruption of data that may be stored there. Move bootmem's allocation map to a location that does not cross any reserved regions Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14609/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: init: Ensure reserved memory regions are not added to bootmemMarcin Nowakowski1-0/+4
Memories managed through boot_mem_map are generally expected to define non-crossing areas. However, if part of a larger memory block is marked as reserved, it would still be added to bootmem allocator as an available block and could end up being overwritten by the allocator. Prevent this by explicitly marking the memory as reserved it if exists in the range used by bootmem allocator. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14608/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Do not request resources for crashkernel if one isn't definedMarcin Nowakowski1-0/+3
When KEXEC is enabled but crashkernel details are not passed through the kernel commandline unnecessary resources are requested (start==end==0) Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: elfcore: add correct copy_regs implementationsMarcin Nowakowski1-0/+6
MIPS does not currently define ELF_CORE_COPY_REGS macros and as a result the generic implementation is used. The generic version attempts to do directly map (struct pt_regs) into (elf_gregset_t), which isn't correct for MIPS platforms and also triggers a BUG() at runtime in include/linux/elfcore.h:16 (BUG_ON(sizeof(*elfregs) != sizeof(*regs))) [ralf@linux-mips.org: Add semicolons to the macro definitions as I do not apply https://patchwork.linux-mips.org/patch/14588/ for now.] Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14586/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Move register dump routines out of ptrace codeMarcin Nowakowski3-32/+49
Current register dump methods for MIPS are implemented inside ptrace methods, but there will be other uses in the kernel for them, so keep them separately in process.c and use those definitions for ptrace instead. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14587/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Kconfig: Fix indentation for kexec-related entriesMarcin Nowakowski1-7/+7
Kconfig entries are not aligned properly, so remove incorrect whitespace. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14631/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: kexec: remove SMP_DUMPMarcin Nowakowski3-25/+2
SMP_DUMP has been added as a new IPI signal when kexec support was added for Cavium Octeon CPUs ('commit 7aa1c8f47e7e ("MIPS: kdump: Add support")'. However, the new signal doesn't appear to ever have a proper handler added (octeon_message_functions[] array has an empty handler for it), and generic IPI handlers now trigger a BUG() on unhandled signal. As the method is unused remove it completely and replace its only invocation with a smp_call_function(). [ralf@linux-mips.org: Renumber SMP_ASK_C0COUNT to avoid numbering gaps.] Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14630/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Add support for ARCH_MMAP_RND_{COMPAT_}BITSMatt Redfearn2-5/+21
arch_mmap_rnd() uses hard-coded limits of 16MB for the randomisation of mmap within 32bit processes and 256MB in 64bit processes. Since v4.4 other arches support tuning this value in /proc/sys/vm/mmap_rnd_bits. Add support for this to MIPS. Set the minimum(default) number of bits randomisation for 32bit to 8 - which with 4k pagesize is unchanged from the current 16MB total randomness. The minimum(default) for 64bit is 12bits, again with 4k pagesize this is the same as the current 256MB. This patch is necessary for MIPS32 to pass the Android CTS tests, with the number of random bits set to 15. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Kees Cook <keescook@chromium.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Daniel Cashman <dcashman@android.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-mips@linux-mips.org Cc: kernel-hardening@lists.openwall.com Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14617/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Lantiq: Activate more drivers in default configurationHauke Mehrtens1-1/+12
This activates the following functionalities: * SMP support (used on xRX200) * PCI support * NAND driver * PHY driver * UART * Watchdog * USB 2.0 controller These driver are driving different IP cores found on the supported SoCs. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14628/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: lantiq: Refresh default configurationHauke Mehrtens1-7/+1
Just generate a configuration based on this default configuration and store it again. This removed some old configuration options. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14629/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03of: Add check to of_scan_flat_dt() before accessing initial_boot_paramsTobias Wolf1-3/+6
An empty __dtb_start to __dtb_end section might result in initial_boot_params being null for arch/mips/ralink. This showed that the boot process hangs indefinitely in of_scan_flat_dt(). Signed-off-by: Tobias Wolf <dev-NTEO@vplace.de> Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14605/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03ralink: Introduce fw_passed_dtb to arch/mips/ralinkTobias Wolf1-2/+10
This patch adds fw_passed_dtb to arch/mips/ralink to support CONFIG_MIPS_RAW_APPENDED_DTB. Furthermore it adds a check that __dtb_start is not the same address as __dtb_end. Signed-off-by: Tobias Wolf <dev-NTEO@vplace.de> Acked-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14662/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Loongson1: Add watchdog support for Loongson1 boardYang Ling6-10/+37
The patch adds watchdog support for Loongson1 board. Signed-off-by: Yang Ling <gnaygnil@gmail.com> Cc: keguang.zhang@gmail.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14644/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Loongson1: Remove several redundant RTC-related macrosYang Ling3-19/+38
Move the RTC-related macros to regs-rtc.h. Signed-off-by: Yang Ling <gnaygnil@gmail.com> Cc: keguang.zhang@gmail.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14642/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Remove RESTORE_ALL_AND_RETPaul Burton1-8/+0
The RESTORE_ALL_AND_RET macro is never used. Remove the dead code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14411/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Allow pre-r6 emulation on SMP MIPSr6 kernelsPaul Burton1-3/+1
There's no reason for the pre-r6 instruction emulation code to be limited to uniprocessor kernels. We already emulate atomic memory access instructions in a way that works for SMP systems, and nothing else should be affected. Remove the artificial limitation, allowing pre-r6 instruction emulation to be used with SMP kernels. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14410/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Cleanup LLBit handling in switch_toPaul Burton1-6/+12
Commit 7c151d3d5d7a ("MIPS: Make use of the ERETNC instruction on MIPS R6") began clearing LLBit during context switches, but did so on all systems where it is writable for unclear reasons & did so from a macro with "software_ll_bit" in its name, which is intended to operate on the ll_bit variable used by ll/sc emulation for old CPUs. We do now need to clear LLBit on MIPSr6 systems where we'll use eretnc to return to userland, but we don't need to do so on MIPSr5 systems with a writable LLBit. Move the clear to its own appropriately named macro, do it only for MIPSr6 systems & comment about why. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14409/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Remove r2_emul_return from struct thread_infoPaul Burton5-22/+4
The r2_emul_return field in struct thread_info was used in order to take an alternate codepath when returning to userland, which (besides not implementing certain features) effectively used the eretnc instruction in place of eret. The difference is that eretnc doesn't clear LLBit, and therefore doesn't cause a linked load & store sequence to fail due to emulation like eret would. The reason eret would usually be used to clear LLBit is so that after context switching we ensure that a load performed by one task doesn't influence another task. However commit 7c151d3d5d7a ("MIPS: Make use of the ERETNC instruction on MIPS R6") which introduced the r2_emul_return field and conditional use of eretnc also for some reason began explicitly clearing LLBit during context switches - despite retaining the use of eret for everything but returns from the pre-r6 instruction emulation code. As LLBit is cleared upon context switches anyway, simplify this by using eretnc unconditionally for MIPSr6 kernels. This allows us to remove the 4 byte r2_emul_return boolean from struct thread_info, simplify the return to user code in entry.S and avoid the overhead of tracking & checking state which we don't need. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14408/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: DTS: img: add device tree for Marduk boardRahul Bedarkar4-0/+188
Add support for Imagination Technologies' Marduk board which is based on Pistachio SoC. It is also known as Creator Ci40. Marduk is legacy name and will be there for decades. Documentation for this board can be found on https://docs.creatordev.io/ci40/ This patch adds initial support for board with following peripherals: * PWM based heartbeat LED * GPIO based buttons * SPI NOR flash on SPI1 * UART0 and UART1 * SD card * Ethernet * USB * PWM * ADC * I2C Signed-off-by: Rahul Bedarkar <rahul.bedarkar@imgtec.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: James Hartley <james.hartley@imgtec.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14394/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: DTS: Add base device tree for Pistachio SoCRahul Bedarkar2-1/+925
Add support for the base Device Tree for Imagination Technologies' Pistachio SoC. This commit supports the following peripherals: * Clocks * Pinctrl and GPIO * UART * SPI * I2C * PWM * ADC * Watchdog * Ethernet * MMC * DMA engine * Crypto * I2S * SPDIF * Internal DAC * Timer * USB * IR * Interrupt Controller Signed-off-by: Rahul Bedarkar <rahul.bedarkar@imgtec.com> Acked-by: James Hartley <james.hartley@imgtec.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14393/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: traps: Ensure L1 & L2 ECC checking match for CM3 systemsPaul Burton2-3/+67
On systems with CM3, we must ensure that the L1 & L2 ECC enables are set to the same value. This is presumed by the hardware & cache corruption can occur when it is not the case. Support enabling & disabling the L2 ECC checking on CM3 systems where this is controlled via a GCR, and ensure that it matches the state of L1 ECC checking. Remove I6400 from the switch statement it will no longer hit, and which was incorrect since the L2 ECC enable bit isn't in the CP0 ErrCtl register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14413/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: R2-on-R6 MULTU/MADDU/MSUBU emulation bugfixLeonid Yegoshin1-6/+6
MIPS instructions MULTU, MADDU and MSUBU emulation requires registers HI/LO to be converted to signed 32bits before 64bit sign extension on MIPS64. Bug was found on running MIPS32 R2 test application on MIPS64 R6 kernel. Fixes: b0a668fb2038 ("MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6") Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Reported-by: Nikola.Veljkovic@imgtec.com Cc: paul.burton@imgtec.com Cc: yamada.masahiro@socionext.com Cc: akpm@linux-foundation.org Cc: andrea.gelmini@gelma.net Cc: macro@imgtec.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14043/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Loongson1B: Modify DEFAULT_MEMSIZEKelvin Cheung1-1/+1
This patch changes DEFAULT_MEMSIZE to 64MB which is the memory size of latest EVB. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13856/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: Loongson1C: Remove ARCH_WANT_OPTIONAL_GPIOLIBKelvin Cheung1-1/+0
This patch removes ARCH_WANT_OPTIONAL_GPIOLIB due to upstream changes. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: Yang Ling <gnaygnil@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13855/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: BMIPS: Migrate interrupts during bmips_cpu_disableFlorian Fainelli1-0/+1
While we properly disabled the per-CPU timer interrupt, we also need to make sure that all interrupts that can possibly have this CPU in their smp_affinity mask also have a chance to see this interrupt migrated to a CPU not being taken offline. [ralf@linux-mips.org: Fix merge conflict.] Fixes: 230b6ff57552 ("MIPS: BMIPS: Mask off timer IRQs when hot-unplugging a CPU") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: cernekee@gmail.com Cc: jaedon.shin@gmail.com Cc: justinpopo6@gmail.com Cc: tglx@linutronix.de Cc: marc.zyngier@arm.com Cc: jason@lakedaemon.net Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14488/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: xilfpga: Update defconfigZubair Lutfullah Kakakhel1-1/+36
Update defconfig to enable emaclite, i2c and temp sensor on the xilfpga platform Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14595/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: xilfpga: Add DT node for AXI emacliteZubair Lutfullah Kakakhel1-0/+26
The xilfpga platform has a Xilinx AXI emaclite block. Add the DT node to use it. Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14596/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: xilfpga: Add DT node for AXI I2CZubair Lutfullah Kakakhel1-0/+22
The xilfpga platform has an AXI I2C Bus master with a temperature sensor connected to it. Add the device tree node to use them. Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14594/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: xilfpga: Update DT node and specify uart irqZubair Lutfullah Kakakhel1-0/+3
Update the DT node with the UART irq Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14593/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: xilfpga: Use Xilinx Interrupt ControllerZubair Lutfullah Kakakhel2-0/+13
IRQs from peripherals such as i2c/uart/ethernet come via the AXI Interrupt controller. Select it in Kconfig for xilfpga and add the DT node Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14592/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: xilfpga: Use irqchip instead of the legacy wayZubair Lutfullah Kakakhel1-5/+2
This prepares the code to use the Xilinx Interrupt Controller driver in drivers/irqchip/irq-xilinx-intc.c Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: Zubair.Kakakhel@imgtec.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14591/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-01-03MIPS: ath79: Fix error handlingChristophe JAILLET1-1/+1
'clk_register_fixed_rate()' returns an error pointer in case of error, not NULL. So test it with IS_ERR. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Aban Bedel <albeu@free.fr> Cc: antonynpavlov@gmail.com Cc: hackpascal@gmail.com Cc: amitoj1606@gmail.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: kernel-janitors@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14464/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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