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2022-07-25cxl/region: Program target listsDan Williams4-11/+259
2022-07-25cxl/region: Attach endpoint decodersDan Williams5-12/+394
2022-07-25cxl/acpi: Add a host-bridge index lookup mechanismDan Williams2-0/+18
2022-07-25cxl/region: Enable the assignment of endpoint decoders to regionsDan Williams6-2/+340
2022-07-25cxl/region: Allocate HPA capacity to regionsDan Williams4-1/+183
2022-07-25cxl/region: Add interleave geometry attributesBen Widawsky3-0/+188
2022-07-25cxl/region: Add a 'uuid' attributeBen Widawsky3-0/+153
2022-07-21cxl/region: Add region creation supportBen Widawsky9-0/+311
2022-07-21resource: Introduce alloc_free_mem_region()Dan Williams3-35/+150
2022-07-21cxl/mem: Enumerate port targets before adding endpointsDan Williams3-29/+47
2022-07-21cxl/hdm: Add sysfs attributes for interleave ways + granularityBen Widawsky2-0/+50
2022-07-21cxl/port: Move dport tracking to an xarrayDan Williams3-56/+47
2022-07-21cxl/port: Move 'cxl_ep' references to an xarray per portDan Williams2-34/+30
2022-07-21cxl/port: Record parent dport when adding portsDan Williams4-20/+27
2022-07-21cxl/port: Record dport in endpoint referencesDan Williams2-17/+37
2022-07-21cxl/hdm: Add support for allocating DPA to an endpoint decoderDan Williams4-2/+295
2022-07-21cxl/hdm: Track next decoder to allocateDan Williams3-0/+18
2022-07-21cxl/hdm: Add 'mode' attribute to decoder objectsDan Williams4-0/+55
2022-07-21cxl/hdm: Enumerate allocated DPADan Williams3-11/+149
2022-07-21cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams4-17/+48
2022-07-21cxl/core: Define a 'struct cxl_root_decoder'Dan Williams3-13/+76
2022-07-21cxl/acpi: Track CXL resources in iomem_resourceDan Williams3-3/+149
2022-07-21cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams5-91/+191
2022-07-19Documentation/cxl: Use a double line break between entriesDan Williams1-0/+16
2022-07-19cxl/port: Read CDAT tableIra Weiny5-0/+244
2022-07-19driver-core: Introduce BIN_ATTR_ADMIN_{RO,RW}Ira Weiny1-0/+16
2022-07-19cxl/pci: Create PCI DOE mailbox's for memory devicesIra Weiny3-0/+48
2022-07-19PCI/DOE: Add DOE mailbox support functionsJonathan Cameron6-1/+646
2022-07-19PCI: Replace magic constant for PCI Sig Vendor IDIra Weiny1-1/+1
2022-07-19PCI: Add vendor ID for the PCI SIGJonathan Cameron1-0/+1
2022-07-11cxl/pmem: Delete unused nvdimm attributeDan Williams1-1/+0
2022-07-10cxl/hdm: Initialize decoder type for memory expander devicesDan Williams1-5/+11
2022-07-10cxl/port: Cache CXL host bridge dataDan Williams2-1/+19
2022-07-10tools/testing/cxl: Fix decoder default stateDan Williams1-1/+0
2022-07-10tools/testing/cxl: Add partition supportDan Williams4-69/+36
2022-07-10tools/testing/cxl: Expand CFMWS windowsDan Williams1-5/+5
2022-07-10tools/testing/cxl: Move cxl_test resources to the top of memoryDan Williams1-1/+2
2022-07-10cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem'Dan Williams4-0/+53
2022-07-10cxl/debug: Move debugfs init to cxl_core_init()Dan Williams3-12/+13
2022-07-09cxl/Documentation: List attribute permissionsDan Williams1-40/+41
2022-07-09cxl/hdm: Require all decoders to be enumeratedBen Widawsky1-9/+3
2022-07-09cxl/mem: Convert partition-info to resourcesDan Williams5-41/+55
2022-07-09cxl: Introduce cxl_to_{ways,granularity}Dan Williams3-41/+54
2022-07-09cxl/core: Drop is_cxl_decoder()Dan Williams2-7/+0
2022-07-09cxl/core: Drop ->platform_res attribute for root decodersDan Williams4-41/+18
2022-07-09cxl/core: Rename ->decoder_range ->hpa_rangeDan Williams4-6/+6
2022-07-09cxl/hdm: Use local hdm variableBen Widawsky1-2/+1
2022-07-09cxl/port: Keep port->uport valid for the entire life of a portDan Williams1-2/+2
2022-06-28tools/testing/cxl: Fix cxl_hdm_decode_init() calling conventionDan Williams1-3/+5
2022-06-28cxl/mbox: Fix missing variable payload checks in cmd size validationVishal Verma1-2/+4