summaryrefslogtreecommitdiffstats
AgeCommit message (Collapse)AuthorFilesLines
2016-06-30clk: highbank: Migrate to clk_hw based registration and OF APIsStephen Boyd1-5/+4
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers in this driver, allowing us to move closer to a clear split of consumer and provider clk APIs. Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-30Merge branch 'clk-st-critical' into clk-nextStephen Boyd3-14/+27
* clk-st-critical: clk: st: clkgen-pll: Detect critical clocks clk: st: clkgen-fsyn: Detect critical clocks clk: st: clk-flexgen: Detect critical clocks
2016-06-30clk: st: clkgen-pll: Detect critical clocksLee Jones1-10/+17
Utilise the new Critical Clock infrastructure to mark clocks which much not be disabled as CRITICAL. Clocks are marked as CRITICAL using clk flags. This patch also ensures flags are peculated through the framework in the correct manner. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-30clk: st: clkgen-fsyn: Detect critical clocksLee Jones1-3/+7
Utilise the new Critical Clock infrastructure to mark clocks which much not be disabled as CRITICAL. Clocks are marked as CRITICAL using clk flags. This patch also ensures flags are peculated through the framework in the correct manner. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-30clk: st: clk-flexgen: Detect critical clocksLee Jones1-1/+3
Utilise the new Critical Clock infrastructure to mark clocks which much not be disabled as CRITICAL. While we're at it, reduce the coverage of the flex_flags variable, since it's only really used in a single for() loop. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-30Merge branch 'clk-hi6220-rtc' into clk-nextStephen Boyd2-2/+5
* clk-hi6220-rtc: clk: hi6220: Add RTC clock for pl031
2016-06-30clk: hi6220: Add RTC clock for pl031Zhangfei Gao2-2/+5
Adds clk support for the pl031 RTC on hi6220 Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> [jstultz: Forward ported, tweaked commit description] Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-29Merge 'clk-notify' into clk-nextStephen Boyd1-2/+14
* clk-notify: clk: Provide notifier stubs when !COMMON_CLK
2016-06-29Merge tag 'clk-renesas-for-v4.8-tag2' of ↵Stephen Boyd5-1/+17
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull second batch of Renesas clk driver updates from Geert Uytterhoeven: - Add support for R-Car V2H, - Add FDP1, DRIF, and thermal clocks on R-Car H3, - Correct a wrong parent clock. * tag 'clk-renesas-for-v4.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7795: Add THS/TSC clock clk: renesas: r8a7795: Add DRIF clock clk: renesas: r8a7795: Correct lvds clock parent clk: renesas: r8a7795: Provide FDP1 clocks clk: renesas: Add R8A7792 support clk: renesas: mstp: Document R8A7792 support clk: renesas: rcar-gen2: Document R8A7792 support
2016-06-28clk: Provide notifier stubs when !COMMON_CLKKrzysztof Kozlowski1-2/+14
The clk notifier symbols are hidden by COMMON_CLK. However on some platforms HAVE_CLK might be set while COMMON_CLK not which leads to compile test build errors like: $ make.cross ARCH=sh drivers/devfreq/tegra-devfreq.c: In function 'tegra_actmon_rate_notify_cb': >> drivers/devfreq/tegra-devfreq.c:391:16: error: 'POST_RATE_CHANGE' undeclared (first use in this function) if (action != POST_RATE_CHANGE) ^ drivers/devfreq/tegra-devfreq.c: In function 'tegra_devfreq_probe': >> drivers/devfreq/tegra-devfreq.c:654:8: error: implicit declaration of function 'clk_notifier_register' [-Werror=implicit-function-declaration] err = clk_notifier_register(tegra->emc_clock, &tegra->rate_change_nb); ^ Export the macros and data type declarations outside of COMMON_CLK ifdef and provide stubs to fix the compile testing. Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-28Merge tag 'clk-renesas-for-v4.8-tag1' of ↵Stephen Boyd10-359/+682
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull support for Renesas R-car M3-W from Geert Uytterhoeven: Add initial support for the Clock Pulse Generator and Module Standby and Software Reset modules on the Renesas R-Car M3-W SoC: - Basic core clocks, - SCIF2 (console) module clock, - INTC-AP (GIC) module clock. * tag 'clk-renesas-for-v4.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Add support for R-Car M3-W clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code clk: renesas: Add r8a7796 CPG Core Clock Definitions clk: renesas: cpg-mssr: Document r8a7796 support
2016-06-28clk: qcom: Remove gcc_aggre1_pnoc_ahb_clk from msm8996Stephen Boyd1-16/+0
This clk is critical to operation of the SoC and should never be turned off. Furthermore, there are no consumers of this clk so let's just delete it so things like eMMC work. Reported-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-22Merge remote-tracking branch 'clk/clk-s905' into clk-nextMichael Turquette15-595/+1844
2016-06-22clk: gxbb: add AmLogic GXBB clk controller driverMichael Turquette5-0/+1245
The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-22clk: gxbb: Document bindings for the GXBB clock controllerMichael Turquette1-0/+36
Add documentations for the clock controller. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-22clk: meson: fractional pll supportMichael Turquette2-2/+45
Fractional MPLLs are a superset of the existing AmLogic MPLLs. They add in a couple of new bitfields for further dividing the clock rate to achieve rates with fractional hertz. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-22clk: meson: add mpll supportMichael Turquette3-1/+105
MPLLs are adjustable rate clocks derived from PLLs. On both Meson8b and GXBB they appear to be only derived from fixed_pll. Add support for these clock types so that they can be added to their respective drivers. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-22clk: meson: add peripheral gate macroMichael Turquette1-0/+14
There are a series of peripheral and system gate clocks that fan out from the clk81 signal. Add a helper macro to statically initialize these gate clocks. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-22clk: meson: only build selected platformsMichael Turquette4-3/+16
Break the AmLogic clock code up so that only the necessary parts are compiled and linked. The core code is selected by both arm and arm64 builds with COMMON_CLK_AMLOGIC. The individual drivers have their own config options as well. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-22clk: meson8b: convert to platform_driverMichael Turquette1-18/+49
This patch creates a proper platform_driver for the meson8b clock controller. Use of CLK_OF_DECLARE is removed, and can be added back in later if very early registration of some clocks is required. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-22clk: meson8b: clean up composite clocksMichael Turquette5-247/+69
Remove the composite clock registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. To preserve git bisect this patch also flips the switch and starts using of_clk_add_hw_provider instead of the deprecated meson_clk_register_clks method. As a byproduct clk.c can be deleted. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-22clk: meson8b: remove mali clkMichael Turquette1-22/+0
This clock is undocumented and always orphaned. Get rid of it until we have more complete clock tree documentation. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-22clk: meson8b: clean up cpu clocksMichael Turquette4-90/+59
Remove the cpu clock registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. Ninja rename a5_clk to cpu_clk to better align with cpufreq convention. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-22clk: meson8b: clean up fixed factor clocksMichael Turquette3-71/+60
Remove the fixed factor registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-22clk: meson8b: clean up pll clocksMichael Turquette4-114/+131
Remove the pll registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-22clk: meson8b: clean up fixed rate clocksMichael Turquette3-75/+54
Remove the fixed_rate registration function and helpers from clkc.[ch]. Replace unnecessary configuration struct with static initialization of the desired clock type. While we're here, begin the transition to a proper platform_driver and call of_clk_add_hw_provider with a shiny new struct clk_hw_onecell_data. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-22clk: meson8b: rectify reg offsets with datasheetMichael Turquette1-3/+12
The register offsets in the data sheet are confusing. Document them more thoroughly. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-21clk: renesas: r8a7795: Add THS/TSC clockKhiem Nguyen1-0/+1
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21clk: renesas: r8a7795: Add DRIF clockRamesh Shanmugasundaram1-0/+8
This patch adds DRIF module clocks for r8a7795 SoC. Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21clk: renesas: r8a7795: Correct lvds clock parentGeert Uytterhoeven1-1/+1
According to the latest information, the parent clock of the LVDS module clock is the S0D4 clock, not the S2D1 clock. Note that this change has no influence on actual operation, as the rcar-du LVDS encoder driver doesn't use the parent clock's rate. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-06-21clk: renesas: r8a7795: Provide FDP1 clocksKieran Bingham1-0/+3
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kieran Bingham <kieran@bingham.xyz> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21clk: renesas: Add R8A7792 supportSergei Shtylyov2-0/+2
Renesas R-Car V2H (R8A7792) clocks are handled by R-Car gen2 clock driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21clk: renesas: mstp: Document R8A7792 supportSergei Shtylyov1-0/+1
Renesas R8A7792 SoC also has the CPG MSTP clocks... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21clk: renesas: rcar-gen2: Document R8A7792 supportSergei Shtylyov1-0/+1
Renesas R8A7792 SoC is a member of the R-Car gen2 family and so has CPG... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-20Merge tag 'clk-samsung-4.8' of git://linuxtv.org/snawrocki/samsung into clk-nextStephen Boyd24-514/+812
Merge changes from Sylwester Nawrocki for samsung clk drivers: - a fix for exynos7 to prevent gating some critical CMU clocks, - addition of CPU clocks for CPU frequency scaling on Exynos5433 SoCs, - additions for exynos5410 SoC required for Odroid XU board support, - register accessors fixes for kernels built for big endian operation (mostly exynos4 SoCs), - Exynos5433 clock definitions fixes required for suspend to RAM and the audio subsystem operation, - many cleanups changing attributes of the clock initializer data * tag 'clk-samsung-4.8' of git://linuxtv.org/snawrocki/samsung: (41 commits) clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE device clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flags to avoid hang during S2R clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD UART clk: samsung: exynos4: fixup reg access on be clk: samsung: fixup endian in pll clk clk: samsung: exynos5410: Add WDT, ACLK266 and SSS clocks clk: samsung: exynos5433: add CPU clocks configuration data and instantiate CPU clocks clk: samsung: cpu: prepare for adding Exynos5433 CPU clocks clk: samsung: exynos5433: prepare for adding CPU clocks clk: samsung: Suppress unbinding to prevent theoretical attacks clk: samsung: exynos5420: Set ID for aclk333 gate clock clk: samsung: exynos5410: Add TMU clock clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks clk: samsung: exynos5410: Add serial3, USB and PWM clocks clk: samsung: exynos3250: Move PLL rates data to init section clk: samsung: Fully constify mux parent names clk: samsung: exynos5250: Move sleep init function to init section clk: samsung: exynos5420: Move sleep init function and PLL data to init section clk: samsung: exynos5433: Move PLL rates data to init section clk: samsung: exynos5433: Constify all clock initializers ...
2016-06-20clk: correct comments for __clk_determine_ratePeng Fan1-3/+1
Correct comments for __clk_determine_rate. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-20clk: vt8500: rework wm8650_find_pll_bits()Roman Volkov1-35/+38
PLL clock on WM8650 is calculated in the following way: M * parent [O1] => / P [O2] => / D [O3] Where O2 is 600MHz >= (M * parent) / P >= 300MHz. Current algorithm does not met this requirement, so that the function may return rates which are not supported by the hardware. This patch fixes the algorithm and simplifies the code, reducing the calculation time by ~10000 times (according to usermode app) by removing the nested loops. Signed-off-by: Roman Volkov <rvolkov@v1ros.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-20clk: vt8500: fix gcc-4.9 warningsArnd Bergmann1-24/+10
This fixes some false positive warnings we get with older compiler versions: clk-vt8500.c: In function ‘wm8650_find_pll_bits’: clk-vt8500.c:430:12: ‘best_div2’ may be used uninitialized in this function clk-vt8500.c:429:12: ‘best_div1’ may be used uninitialized in this function clk-vt8500.c:428:14: ‘best_mul’ may be used uninitialized in this function clk-vt8500.c: In function ‘wm8750_find_pll_bits’: clk-vt8500.c:509:12: ‘best_div2’ may be used uninitialized in this function clk-vt8500.c:508:12: ‘best_div1’ may be used uninitialized in this function clk-vt8500.c:507:14: ‘best_mul’ may be used uninitialized in this function clk-vt8500.c: In function ‘wm8850_find_pll_bits’: clk-vt8500.c:560:12: ‘best_div2’ may be used uninitialized in this function clk-vt8500.c:559:12: ‘best_div1’ may be used uninitialized in this function clk-vt8500.c:558:14: ‘best_mul’ may be used uninitialized in this function As the local variables are only use for temporaries, we can just as well assign the final values directly, which also makes the code slightly shorter. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Roman Volkov <rvolkov@v1ros.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-20clk: Remove unused variableLee Jones1-2/+1
Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-20clk: hi6220: fix missing clk.h includeBen Dooks1-0/+2
Fix the warning from missing "clk.h" include which defines hi6220_register_clkdiv() function. drivers/clk/hisilicon/clkdivider-hi6220.c:102:12: warning: symbol 'hi6220_register_clkdiv' was not declared. Should it be static? Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-20clk: iproc: fix missing include of clk-iproc.hBen Dooks1-0/+2
Fix the implicit declaration of iproc_armpll_setup() by including clk-iproc.h which defines it. Fixes the warning: drivers/clk/bcm/clk-iproc-armpll.c:242:13: warning: symbol 'iproc_armpll_setup' was not declared. Should it be static? Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-20clk: at91: make of_sama5d2_clk_generated_setup() staticBen Dooks1-1/+1
The of_sama5d2_clk_generated_setup() is not exported outside of the driver, so make it static to fix the warning about it being not static: drivers/clk/at91/clk-generated.c:270:13: warning: symbol 'of_sama5d2_clk_generated_setup' was not declared. Should it be static? Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-20Merge branch 'clk-fixes' into clk-nextStephen Boyd4-17/+11
* clk-fixes: clk: Fix return value check in oxnas_stdclk_probe() clk: rockchip: release io resource when failing to init clk on rk3399 clk: rockchip: fix cpuclk registration error handling clk: rockchip: Revert "clk: rockchip: reset init state before mmc card initialization" clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src clk: rockchip: mark rk3399 GIC clocks as critical clk: rockchip: initialize flags of clk_init_data in mmc-phase clock
2016-06-20Merge tag 'v4.7-rockchip-clk-fixes1' of ↵Stephen Boyd3-15/+9
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes A bunch of fixes. Some for the newly added rk3399 clock tree, some concerning error handling and initialization and a revert of the mmc-phase clock initialization, as this could conflict with the bootloader setting of this clock and a real solution to initing the phase correctly from dw_mmc went in as fix for 4.7 through the mmc tree. * tag 'v4.7-rockchip-clk-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: release io resource when failing to init clk on rk3399 clk: rockchip: fix cpuclk registration error handling clk: rockchip: Revert "clk: rockchip: reset init state before mmc card initialization" clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src clk: rockchip: mark rk3399 GIC clocks as critical clk: rockchip: initialize flags of clk_init_data in mmc-phase clock
2016-06-20clk: Fix return value check in oxnas_stdclk_probe()Wei Yongjun1-2/+2
In case of error, the function syscon_node_to_regmap() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Fixes: 0bbd72b4c64f ("clk: Add Oxford Semiconductor OXNAS Standard Clocks") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-20clk: multiplier: Prevent the multiplier from under / over flowingMaxime Ripard1-3/+17
In the current multiplier base clock implementation, if the CLK_SET_RATE_PARENT flag isn't set, the code will not make sure that the multiplier computed remains within the boundaries of our clock. This means that if the clock we want to reach is below the parent rate, or if the multiplier is above the maximum that we can reach, we will end up with a completely bogus one that the clock cannot achieve. Fixes: f2e0a53271a4 ("clk: Add a basic multiplier clock") Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1463402840-17062-3-git-send-email-maxime.ripard@free-electrons.com
2016-06-16Merge commit 'f17a0dd1c2e0' into clk-nextMichael Turquette1-4/+4
2016-06-15clk: Use _rcuidle suffix to allow clk_core_enable() to used from idlePaul E. McKenney1-2/+2
This commit fixes the RCU use-from-idle bug corresponding the following splat: > [ INFO: suspicious RCU usage. ] > 4.6.0-rc5-next-20160426+ #1127 Not tainted > ------------------------------- > include/trace/events/clk.h:45 suspicious rcu_dereference_check() usage! > > other info that might help us debug this: > > > RCU used illegally from idle CPU! > rcu_scheduler_active = 1, debug_locks = 0 > RCU used illegally from extended quiescent state! > 2 locks held by swapper/0/0: > #0: (&oh->hwmod_key#30){......}, at: [<c0121afc>] omap_hwmod_enable+0x18/0x44 > #1: (enable_lock){......}, at: [<c0630684>] clk_enable_lock+0x18/0x124 > > stack backtrace: > CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.6.0-rc5-next-20160426+ #1127 > Hardware name: Generic OMAP36xx (Flattened Device Tree) > [<c0110290>] (unwind_backtrace) from [<c010c3a8>] (show_stack+0x10/0x14) > [<c010c3a8>] (show_stack) from [<c047fd68>] (dump_stack+0xb0/0xe4) > [<c047fd68>] (dump_stack) from [<c06315c0>] (clk_core_enable+0x1e0/0x36c) > [<c06315c0>] (clk_core_enable) from [<c0632298>] (clk_enable+0x1c/0x38) > [<c0632298>] (clk_enable) from [<c01204e0>] (_enable_clocks+0x18/0x7c) > [<c01204e0>] (_enable_clocks) from [<c012137c>] (_enable+0x114/0x2ec) > [<c012137c>] (_enable) from [<c0121b08>] (omap_hwmod_enable+0x24/0x44) > [<c0121b08>] (omap_hwmod_enable) from [<c0122ad0>] (omap_device_enable+0x3c/0x90) > [<c0122ad0>] (omap_device_enable) from [<c0122b34>] (_od_runtime_resume+0x10/0x38) > [<c0122b34>] (_od_runtime_resume) from [<c052cc00>] (__rpm_callback+0x2c/0x60) > [<c052cc00>] (__rpm_callback) from [<c052cc54>] (rpm_callback+0x20/0x80) > [<c052cc54>] (rpm_callback) from [<c052df7c>] (rpm_resume+0x3d0/0x6f0) > [<c052df7c>] (rpm_resume) from [<c052e2e8>] (__pm_runtime_resume+0x4c/0x64) > [<c052e2e8>] (__pm_runtime_resume) from [<c04bf2c4>] (omap2_gpio_resume_after_idle+0x54/0x68) > [<c04bf2c4>] (omap2_gpio_resume_after_idle) from [<c01269dc>] (omap3_enter_idle_bm+0xfc/0x1ec) > [<c01269dc>] (omap3_enter_idle_bm) from [<c0601888>] (cpuidle_enter_state+0x80/0x3d4) > [<c0601888>] (cpuidle_enter_state) from [<c0183b08>] (cpu_startup_entry+0x198/0x3a0) > [<c0183b08>] (cpu_startup_entry) from [<c0b00c0c>] (start_kernel+0x354/0x3c8) > [<c0b00c0c>] (start_kernel) from [<8000807c>] (0x8000807c) Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Cc: Russell King <linux@arm.linux.org.uk> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: <linux-omap@vger.kernel.org> Cc: <linux-arm-kernel@lists.infradead.org> Cc: <linux-clk@vger.kernel.org>
2016-06-15clk: Add _rcuidle tracepoints to allow clk_core_disable() use from idlePaul E. McKenney1-2/+2
This commit adds an _rcuidle suffix to a pair of trace events to prevent the following splat: > =============================== > [ INFO: suspicious RCU usage. ] > 4.6.0-rc5-next-20160426+ #1114 Not tainted > ------------------------------- > include/trace/events/clk.h:59 suspicious rcu_dereference_check() usage! > > other info that might help us debug this: > > > RCU used illegally from idle CPU! > rcu_scheduler_active = 1, debug_locks = 0 > RCU used illegally from extended quiescent state! > 2 locks held by swapper/0/0: > #0: (&oh->hwmod_key#30){......}, at: [<c0121b40>] omap_hwmod_idle+0x18/0x44 > #1: (enable_lock){......}, at: [<c0630998>] clk_enable_lock+0x18/0x124 > > stack backtrace: > CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.6.0-rc5-next-20160426+ #1114 > Hardware name: Generic OMAP36xx (Flattened Device Tree) > [<c0110290>] (unwind_backtrace) from [<c010c3a8>] (show_stack+0x10/0x14) > [<c010c3a8>] (show_stack) from [<c047fd68>] (dump_stack+0xb0/0xe4) > [<c047fd68>] (dump_stack) from [<c0631618>] (clk_core_disable+0x17c/0x348) > [<c0631618>] (clk_core_disable) from [<c0632774>] (clk_disable+0x24/0x30) > [<c0632774>] (clk_disable) from [<c0120590>] (_disable_clocks+0x18/0x7c) > [<c0120590>] (_disable_clocks) from [<c0121680>] (_idle+0x12c/0x230) > [<c0121680>] (_idle) from [<c0121b4c>] (omap_hwmod_idle+0x24/0x44) > [<c0121b4c>] (omap_hwmod_idle) from [<c0122c24>] (omap_device_idle+0x3c/0x90) > [<c0122c24>] (omap_device_idle) from [<c052cc00>] (__rpm_callback+0x2c/0x60) > [<c052cc00>] (__rpm_callback) from [<c052cc54>] (rpm_callback+0x20/0x80) > [<c052cc54>] (rpm_callback) from [<c052d150>] (rpm_suspend+0x100/0x768) > [<c052d150>] (rpm_suspend) from [<c052ec58>] (__pm_runtime_suspend+0x64/0x84) > [<c052ec58>] (__pm_runtime_suspend) from [<c04bf25c>] (omap2_gpio_prepare_for_idle+0x5c/0x70) > [<c04bf25c>] (omap2_gpio_prepare_for_idle) from [<c0125568>] (omap_sram_idle+0x140/0x244) > [<c0125568>] (omap_sram_idle) from [<c01269dc>] (omap3_enter_idle_bm+0xfc/0x1ec) > [<c01269dc>] (omap3_enter_idle_bm) from [<c0601bdc>] (cpuidle_enter_state+0x80/0x3d4) > [<c0601bdc>] (cpuidle_enter_state) from [<c0183b08>] (cpu_startup_entry+0x198/0x3a0) > [<c0183b08>] (cpu_startup_entry) from [<c0b00c0c>] (start_kernel+0x354/0x3c8) > [<c0b00c0c>] (start_kernel) from [<8000807c>] (0x8000807c) Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Cc: Russell King <linux@arm.linux.org.uk> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: <linux-omap@vger.kernel.org> Cc: <linux-arm-kernel@lists.infradead.org> Cc: <linux-clk@vger.kernel.org>
2016-06-10clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE deviceJaehoon Chung2-6/+8
This patch adds the CLK_IGNORE_UNUSED flag for PCI Express's clocks which need to remain enabled. The 'pcie' gate clock definition is also added. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [s.nawrocki@samsung.com: edited the patch's summary] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-02-02 07:43:42 +0000