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2016-01-16clk: rockchip: rk3368: fix some clock gatesJianqun xu1-13/+13
Reference to the Rockchip RK3368 TRM v1.1, some clock gates need to be updated. Signed-off-by: Jianqun xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16clk: rockchip: rk3036: rename emac ext source clockXing Zheng2-2/+2
There is only support rmii in the RK3036, so we should use the correct ext clock name as described in the TRM. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> [update dt-binding document as well] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16clk: rockchip: rk3036: fix the div offset for emac clockXing Zheng1-2/+2
Due to reference to old version TRM, there are incorrect emac clock node. The SEL_21_9 is used for the parent div, the SEL_21_4 is used for the child div. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16clk: rockchip: rk3036: fix uarts clock errorXing Zheng1-4/+4
Due to a copy-paste error the uart1 and uart2 clock div set incorrect, fix it. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16clk: rockchip: rk3036: fix the FLAGs for clock muxXing Zheng1-6/+6
The DFLAGS are used for the clock dividers, the CLKSEL_CON flags of COMPOSITE_NODIV type should be MFLAGS. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-13clk: remove duplicated COMMON_CLK_NXP record from clk/KconfigVladimir Zapolskiy1-5/+0
Presumably the second COMMON_CLK_NXP config option in drivers/clk/Kconfig appeared after a merge conflict resolution, remove the wrong record of two. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-01-04Merge tag 'tegra-for-4.5-clk' of ↵Michael Turquette13-928/+5437
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk: tegra: Changes for v4.5-rc1 This set of changes adds support for the Tegra210 SoC and contains a couple fixes and cleanups.
2016-01-02clk: fix clk-gpio.c with optional clock= DT propertyRussell King1-9/+13
When the clock DT property is not given, of_clk_get_parent_count() returns -ENOENT, which then tries to allocate -2 x 4 bytes of memory, which of course fails, causing the whole driver to fail to create the clock. This causes the SolidRun platforms to fail probing the SDHCI1 interface which is connected to the WiFi. Fix this by detecting errno codes, skipping the allocation, and fixing of_clk_gpio_gate_delayed_register_get() to handle a NULL parent_names array. Fixes: 80eeb1f0f757 ("clk: add gpio controlled clock multiplexer") Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-01-02Merge branch 'clk-rockchip' into clk-nextMichael Turquette4-47/+116
2016-01-02clk: rockchip: fix section mismatches with new child-clocksHeiko Stübner4-47/+116
To model the muxes downstream of fractional dividers we introduced the child property, allowing to describe a direct child clock. The first implementation seems to cause section warnings, as the core clock-tree is marked as initdata while the data pointed to from the child element is not. While there may be some way to also set that missing property in the inline notation I didn't find it, so to actually fix the issue for now move the sub-definitions into separate declarations that can have their own __initdata properties. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-31clk: gpio: handle error codes for of_clk_get_parent_count()Brian Norris1-2/+4
We might make bad memory allocations if we get (e.g.) -ENOSYS from of_clk_get_parent_count(). Noticed by Coverity. Fixes: f66541ba02d5 ("clk: gpio: Get parent clk names in of_gpio_clk_setup()") Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Jyri Sarha <jsarha@ti.com> Cc: Sergej Sawazki <ce3a@gmx.de> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-31clk: gpio: fix memory leakSudip Mukherjee1-1/+3
If we fail to allocate parent_name then we are returning but we missed freeing data which has already been allocated. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-31Merge branch 'clk-renesas' into clk-nextMichael Turquette1-0/+1
2015-12-31clk: shmobile: r8a7795: Add SATA0 clockUlrich Hecht1-0/+1
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24Merge branch 'clk-bcm2835' into clk-nextMichael Turquette2-55/+103
2015-12-24clk: bcm2835: Add PWM clock supportRemi Pommarel2-1/+15
Register the pwm clock for bcm2835. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24clk: bcm2835: Support for clock parent selectionRemi Pommarel1-45/+77
Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple parent clocks. These clocks divide the rate of a parent which can be selected by setting the proper bits in the clock control register. Previously all these parents where handled by a mux clock. But a mux clock cannot be used because updating clock control register to select parent needs a password to be xor'd with the parent index. This patch get rid of mux clock and make these clocks handle their own parent, allowing them to select the one to use. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24clk: bcm2835: add a round up ability to the clock divisorRemi Pommarel1-10/+12
Make bcm2835_clock_choose_div to optionally round up the chosen MASH divisor so that the resulting average rate will not be higher than the requested one. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24Merge branch 'clk-lpc32xx' into clk-nextMichael Turquette7-1/+1690
2015-12-24clk: lpc32xx: add common clock framework driverVladimir Zapolskiy3-0/+1576
Add support for all configurable clocks found on NXP LPC32xx SoC. The list contains several heterogenous groups of clocks: * system clocks including multiple dividers and muxes, * x397 PLL, HCLK PLL and USB PLL, * peripheral clocks inherited from rtc, hclk and pclk, * USB controller clocks: AHB slave, I2C, OTG, OHCI and device. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24clk: lpc18xx: add NXP specific COMMON_CLK_NXP configuration symbolVladimir Zapolskiy2-1/+6
The change adds COMMON_CLK_NXP configuration symbol and enables it for NXP LPC18XX architecture, this is needed to reuse drivers/clk/nxp folder for NXP common clock framework drivers other than LPC18XX one. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24dt-bindings: clock: add NXP LPC32xx clock list for consumersVladimir Zapolskiy1-0/+56
The change adds a list of NXP LPC32xx clocks, which can be requested by clock consumers. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24dt-bindings: clock: add description of LPC32xx USB clock controllerVladimir Zapolskiy1-0/+22
NXP LPC32xx USB controller has a subdevice, which controls USB AHB slave, USB OTG, USB OHCI, USB device and I2C controller to USB phy clocks, this change adds description of the clock controller, for more details reference LPC32xx User's Manual, namely USB control, OTG clock control and OTG clock status registers. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24dt-bindings: clock: add description of LPC32xx clock controllerVladimir Zapolskiy1-0/+30
NXP LPC32xx SoC has a clocking and power control unit (CPC) as a part of system control block (SCB). CPC is supplied by two external oscillators and it manages core and most of peripheral clocks, the change adds description of DT bindings for clock controller found on LPC32xx SoC series. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23Merge tag 'sunxi-clocks-for-4.5' of ↵Michael Turquette9-12/+638
https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner clocks changes for 4.5 Clock patches for the Allwinner SoCs: - H3 clocks - A10/A20 Video Engine clocks - DRAM gates - A80 special CPU clock
2015-12-23Merge branch 'clk-rockchip' into clk-nextMichael Turquette7-105/+254
2015-12-23clk: rockchip: rk3036: include downstream muxes into fractional dividersXing Zheng1-17/+17
Use the newly introduced possibility to combine the fractional dividers with their downstream muxes for all fractional dividers on currently supported RK3036 SoCs. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23clk: add flag for clocks that need to be enabled on rate changesHeiko Stuebner2-0/+19
Some clocks need to be enabled to accept rate changes. This patch adds a new flag CLK_SET_RATE_UNGATE that lets clk_change_rate enable the clock before trying to change the rate and disable it again afterwards. This of course doesn't effect clocks that are already running at that point, as their refcount will only temporarily increase. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23clk: rockchip: Allow the RK3288 SPDIF clocks to change their parentSjoerd Simons1-8/+8
The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288 SoCs only feed those clocks, allow those clocks to change their parents all the way up the hierarchy. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23clk: rockchip: include downstream muxes into fractional dividersHeiko Stuebner2-72/+74
Use the newly introduced possibility to combine the fractional dividers with their downstream muxes for all fractional dividers on currently supported Rockchip SoCs. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23clk: rockchip: handle mux dependency of fractional dividersHeiko Stuebner2-14/+142
The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-22Merge branch 'clk-bcm2835' into clk-nextMichael Turquette4-0/+134
2015-12-22clk: bcm2835: Add a driver for the auxiliary peripheral clock gates.Eric Anholt2-0/+86
There are a pair of SPI masters and a mini UART that were last minute additions. As a result, they didn't get integrated in the same way as the other gates off of the VPU clock in CPRMAN. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-22clk: bcm2835: Add bindings for the auxiliary peripheral clock gates.Eric Anholt2-0/+48
These will be used for enabling UART1, SPI1, and SPI2. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-22Merge branch 'clk-dove' into clk-nextMichael Turquette4-1/+275
2015-12-22clk: add Dove PLL divider support for GPU, VMeta and AXI clocksRussell King4-1/+275
Add support for the Dove PLL dividers, which are used to generate the clocks for the AXI bus, as well as the GPU and VMeta peripherals. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-22Merge tag 'clk-samsung-4.5' of git://linuxtv.org/snawrocki/samsung into clk-nextMichael Turquette4-13/+102
drivers/clk/samsung updates (mostly bug fixes): - instantiation of the cpu clocks and addition of the GSCL IP parent clocks to the list of available consumer clocks for exynos542x SoCs; - MFC IP parent clock fix for exynos542x; - fix of locking bug in samsung/clk-cpu.c which caused system crashes with cpufreq enabled; - minor cleanup for s3c2410.
2015-12-22Merge commit 'fe5fa8fbd4d47f40a45fa29ee1abdb10cb061ec2' into clk-nextMichael Turquette78-243/+11938
2015-12-22Merge tag 'imx-clk-v4.5' of ↵Michael Turquette7-29/+32
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next The i.MX clock updates for 4.5: - Add is_prepared function callback for pllv3 clock driver - Use imx_check_clocks() on imx6ul and imx7d clock drivers to save some code - Add a core clock for imx7d to support generic cpufreq driver - Support imx6q clock routing with OSC to anaclk2/2b - To support more precise pixel clocks on imx5, allow ipu_di_sel clock selectors to influence the PLLs that they are derived from - A cleanup on imx25 OSC clock
2015-12-22Merge tag 'v4.5-rockchip-clk1_1' of ↵Michael Turquette15-33/+2025
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Rockchip clock changes for 4.5 containing - a new pll-type used on rk3036 and other Cortex-A7 socs - new clock-trees for rk3036 and rk3228 - switch rk3288 plls to slow mode on reboot - a bunch of new clock ids - some more critical clocks - wrong register offsets for the rk3368 cpuclks - allowing more than 2 parents for the cpuclk
2015-12-22Merge branch 'clk-shmobile-for-v4.5' of ↵Michael Turquette8-63/+1220
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
2015-12-22clk: fix codying style of if ... else blocksMasahiro Yamada1-3/+2
This code is unreadable due to the blank line between if and else blocks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-21clk: rockchip: only enter pll slow-mode directly before reboots on rk3288Heiko Stuebner7-8/+13
As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") states, switching the PLLs to slow-mode is only necessary when rebooting using the soft-reset done through the CRU. The dwc2 controllers used create really big number of interrupts in special constellations involving usb-hubs and their number is so high, it can even overwhelm the interrupt handler if the cpu-speed os to low. Right now the PLLs are put into slow-mode in a shutdown syscore_ops callback which means it happens on all reboots (not only the soft-reset ones) and even on poweroff actions. This can result in the system not powering off and getting stuck instead, so we should move the slow-mode change nearer to the actual reboot action. For this we introduce the possiblity to also set a callback that gets called from the restart-handler directly prior to restarting the system and move the shutdown-callback to this new option. With this the slow-mode switch is done only on the necessary reboots and also has a smaller possibility of causing artifacts. Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2015-12-20Linux 4.4-rc6v4.4-rc6Linus Torvalds1-1/+1
2015-12-20Merge tag 'rtc-4.4-3' of ↵Linus Torvalds2-14/+53
git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux Pull RTC fixes from Alexandre Belloni: "Late fixes for the RTC subsystem for 4.4: A fix for a nasty hardware bug in rk808 and an initialization reordering in da9063 to fix a possible crash" * tag 'rtc-4.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: rtc: da9063: fix access ordering error during RTC interrupt at system power on rtc: rk808: Compensate for Rockchip calendar deviation on November 31st
2015-12-20rtc: da9063: fix access ordering error during RTC interrupt at system power onSteve Twiss1-10/+9
This fix alters the ordering of the IRQ and device registrations in the RTC driver probe function. This change will apply to the RTC driver that supports both DA9063 and DA9062 PMICs. A problem could occur with the existing RTC driver if: A system is started from a cold boot using the PMIC RTC IRQ to initiate a power on operation. For instance, if an RTC alarm is used to start a platform from power off. The existing driver IRQ is requested before the device has been properly registered. i.e. ret = devm_request_threaded_irq() comes before rtc->rtc_dev = devm_rtc_device_register(); In this case, the interrupt can be called before the device has been registered and the handler can be called immediately. The IRQ handler da9063_alarm_event() contains the function call rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF); which in turn tries to access the unavailable rtc->rtc_dev. The fix is to reorder the functions inside the RTC probe. The IRQ is requested after the RTC device resource has been registered so that get_irq_byname is the last thing to happen. Signed-off-by: Steve Twiss <stwiss.opensource@diasemi.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2015-12-20rtc: rk808: Compensate for Rockchip calendar deviation on November 31stJulius Werner1-4/+44
In A.D. 1582 Pope Gregory XIII found that the existing Julian calendar insufficiently represented reality, and changed the rules about calculating leap years to account for this. Similarly, in A.D. 2013 Rockchip hardware engineers found that the new Gregorian calendar still contained flaws, and that the month of November should be counted up to 31 days instead. Unfortunately it takes a long time for calendar changes to gain widespread adoption, and just like more than 300 years went by before the last Protestant nation implemented Greg's proposal, we will have to wait a while until all religions and operating system kernels acknowledge the inherent advantages of the Rockchip system. Until then we need to translate dates read from (and written to) Rockchip hardware back to the Gregorian format. This patch works by defining Jan 1st, 2016 as the arbitrary anchor date on which Rockchip and Gregorian calendars are in sync. From that we can translate arbitrary later dates back and forth by counting the number of November/December transitons since the anchor date to determine the offset between the calendars. We choose this method (rather than trying to regularly "correct" the date stored in hardware) since it's the only way to ensure perfect time-keeping even if the system may be shut down for an unknown number of years. The drawback is that other software reading the same hardware (e.g. mainboard firmware) must use the same translation convention (including the same anchor date) to be able to read and write correct timestamps from/to the RTC. Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2015-12-19Merge tag 'tty-4.4-rc6' of ↵Linus Torvalds5-17/+19
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty Pull tty/serial fixes from Greg KH: "Here are some tty/serial driver fixes for 4.4-rc6 that resolve some reported problems. All of these have been in linux-next. The details are in the shortlog" * tag 'tty-4.4-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: tty: Fix GPF in flush_to_ldisc() serial: earlycon: Add missing spinlock initialization serial: sh-sci: Fix length of scatterlist n_tty: Fix poll() after buffer-limited eof push read serial: 8250_uniphier: fix dl_read and dl_write functions
2015-12-19Merge tag 'usb-4.4-rc6' of ↵Linus Torvalds11-47/+122
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB fixes from Greg KH: "Here are some USB and PHY fixes for 4.4-rc6. All of them resolve some reported problems. Full details in the shortlog" * tag 'usb-4.4-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: USB: fix invalid memory access in hub_activate() USB: ipaq.c: fix a timeout loop phy: core: Get a refcount to phy in devm_of_phy_get_by_index() phy: cygnus: pcie: add missing of_node_put phy: miphy365x: add missing of_node_put phy: miphy28lp: add missing of_node_put phy: rockchip-usb: add missing of_node_put phy: berlin-sata: add missing of_node_put phy: mt65xx-usb3: add missing of_node_put phy: brcmstb-sata: add missing of_node_put phy: sun9i-usb: add USB dependency
2015-12-19Merge tag 'md/4.4-rc5-fixes' of git://neil.brown.name/mdLinus Torvalds3-10/+24
Pull md fixes from Neil Brown: "Four fixes for md: - two recently introduced regressions fixed. - one older bug in RAID10 - tagged for -stable since 4.2 - one minor sysfs api improvement" * tag 'md/4.4-rc5-fixes' of git://neil.brown.name/md: Fix remove_and_add_spares removes drive added as spare in slot_store md: fix bug due to nested suspend MD: change journal disk role to disk 0 md/raid10: fix data corruption and crash during resync
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-07 22:37:40 +0000