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2017-01-26clk: mediatek: Fix MT8135 dependenciesJean Delvare1-2/+2
The MT8135 is a 32-bit SoC, so only propose it on ARM architecture, not ARM64. Signed-off-by: Jean Delvare <jdelvare@suse.de> Fixes: 234d511d8c15 ("clk: mediatek: Add hardware dependency") Cc: Andreas Färber <afaerber@suse.de> Acked-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: mediatek: Fix MT2701 dependenciesJean Delvare1-7/+8
If I say "no" to "Clock driver for Mediatek MT2701", I don't want to be asked individually about each sub-driver. No means no. Additionally, this driver shouldn't be proposed at all on non-mediatek builds, unless build-testing. Signed-off-by: Jean Delvare <jdelvare@suse.de> Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: James Liao <jamesjj.liao@mediatek.com> Cc: Shunli Wang <shunli.wang@mediatek.com> Cc: Erin Lo <erin.lo@mediatek.com> Cc: Michael Turquette <mturquette@baylibre.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: ti: divider: Add the table parsing to get the best divider valueKeerthy1-1/+30
Currently the divider selection logic blindly divides the parent_rate by the clk rate and gives the divider value for the divider clocks which do not have the CLK_SET_RATE_PARENT flag set. Add the clk divider table parsing to get the closest divider available in the table provided via Device tree. The code is pretty much taken from: drivers/clk/clk-divider.c. and used here to fix up the best divider selection logic. Signed-off-by: Keerthy <j-keerthy@ti.com> Reported-by: Richard Woodruff <r-woodruff2@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: qcom: gdsc: Fix handling of hw control enable/disableRajendra Nayak1-13/+45
Once a gdsc is brought in and out of HW control, there is a power down and up cycle which can take upto 1us. Polling on the gdsc status immediately after the hw control enable/disable can mislead software/firmware to belive the gdsc is already either on or off, while its yet to complete the power cycle. To avoid this add a 1us delay post a enable/disable of HW control mode. Also after the HW control mode is disabled, poll on the status to check gdsc status reflects its 'on' before force disabling it in software. Reported-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Reviewed-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Tested-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Fixes: 904bb4f5c7de ("clk: qcom: gdsc: Add support for gdscs with HW control") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: meson8b: fix clk81 register addressJerome Brunet1-1/+0
During meson8b clock probe, clk81 register address is fixed twice. First using the meson8b_clk_gates array, then by directly changing meson8b_clk81 register. As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base + clk_base. Fixed by just removing the second fixup. Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: stm32f7: Introduce stm32f7 clocks for STM32F746 boardsGabriel Fernandez1-6/+271
This patch enables clocks for STM32F746 boards. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26Merge branch 'clk-stm32f4' into clk-nextStephen Boyd2-0/+40
* clk-stm32f4: clk: stm32f7: Add stm32f7 clock DT bindings for STM32F746 boards
2017-01-26clk: uniphier: continue probing even if some clocks fail to registerMasahiro Yamada1-5/+2
Do not let the entire probe function fail even if some clocks fail to register. Let's continue with succeeded clocks. This will give the system more chances to boot and allow us to investigate the cause of the failure. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26Merge branch 'clk-imx7', 'clk-bcm2835' into clk-nextStephen Boyd5-51/+273
* clk-imx7: clk: imx7d: Add the OCOTP clock * clk-bcm2835: clk: bcm2835: Add leaf clock measurement support, disabled by default clk: bcm2835: Register the DSI0/DSI1 pixel clocks. clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.
2017-01-20clk: stm32f7: Add stm32f7 clock DT bindings for STM32F746 boardsGabriel Fernandez2-0/+40
This patch introduces the stm32f7 clock DT bindings. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: imx7d: Add the OCOTP clockFabio Estevam2-1/+3
Add the OCOTP so that this hardware block can be used. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: bcm2835: Add leaf clock measurement support, disabled by defaultEric Anholt1-25/+119
This proved incredibly useful during debugging of the DSI driver, to see if our clocks were running at rate we requested. Let's leave it here for the next person interacting with clocks on the platform (and so that hopefully we can just hook it up to debugfs some day). Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: bcm2835: Register the DSI0/DSI1 pixel clocks.Eric Anholt3-13/+125
The DSI pixel clocks are muxed from clocks generated in the analog phy by the DSI driver. In order to set them as parents, we need to do the same name lookup dance on them as we do for our root oscillator. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.Eric Anholt1-14/+28
Our core PLLs are intended to be configured once and left alone. With the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would change PLLD just to get closer to the requested DSI clock, thus changing PLLD_PER, the UART and ethernet PHY clock rates downstream of it, and breaking ethernet. We *do* want PLLH to change so that PLLH_AUX can be exactly the value we want, though. Thus, we need to have a per-divider policy of whether to pass rate changes up. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: cs2000: add Suspend/Resume featureKhiem Nguyen1-0/+22
CS2000 needs re-setup when redume, otherwise, it can't handle correct clock rate. Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com> [Kuninori: cleanup original patch] Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933Marek Vasut4-0/+807
Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These chips have two clock inputs, XTAL or CLK, which are muxed into single PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip while the 5P49V5923 requires external XTAL. The PLL feeds two fractional dividers. Each fractional divider feeds output mux, which allows selecting between clock from the fractional divider itself or from output mux on output N-1. In case of output mux 0, the output N-1 is instead connected to the output from the mux feeding the PLL. The driver thus far supports only the 5P49V5923 and 5P49V5933, while it should be easily extensible to the whole 5P49V59xx family of chips as they are all pretty similar. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: vc5: Add bindings for IDT VersaClock 5P49V5923 and 5P49V5933Marek Vasut1-0/+65
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These are I2C clock generators with optional clock source from either XTal or dedicated clock generator and, depending on the model, two or more clock outputs. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20Merge tag 'v4.11-rockchip-clk1' of ↵Stephen Boyd13-13/+1533
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk updates from Heiko Stuebner: A new clock-type for the 1-2 muxes per soc that are for whatever reason controlled through the General Register Files, support for the rk3328 clock-controller (including a new pll-type) and the usual clock ids and some fixes. * tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: clk: add rockchip,grf property for RK3399 clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: use rk3288 isp_in clock ids clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: add rk3288 isp_in clock ids clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFER clk: rockchip: add clock controller for rk3328 dt-bindings: add bindings for rk3328 clock controller clk: rockchip: add dt-binding header for rk3328 clk: rockchip: add new pll-type for rk3328 clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288 clk: rockchip: add a clock-type for muxes based in the grf
2017-01-20Merge tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung into ↵Stephen Boyd7-1439/+18
clk-next Pull Samsung clk updates from Sylwester Nawrocki: - addition of the CPU clock configuration data for Exynos4412 Prime SoC variant, - removal of driver for deprecated Exynos4415 SoC, - switching from the syscore to regular system sleep PM ops in the audio subsystem clocks controller driver, - updates of the definitions of some "Network On Chip" related clocks. * tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung: clk: samsung: Remove Exynos4415 driver (SoC not supported anymore) clk: samsung: exynos-audss: Replace syscore PM with platform device PM clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as critical clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
2017-01-20clk: imx6: don't restrict LDB mux changes on QuadPlusLucas Stach1-8/+13
The LDB mux/gate layout has been fixed on QuadPlus, so there is no need to restrict the LDB mux changes on this hardware, as the erratum preventing this from working properly is gone. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20Merge tag 'clk-renesas-for-v4.11-tag1' of ↵Stephen Boyd1-0/+9
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull renesas clk updates from Geert Uytterhoeven: - Add CAN and MSIOF related clocks for R-Car M3-W. * tag 'clk-renesas-for-v4.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add MSIOF controller clocks clk: renesas: r8a7796: Add CAN FD peripheral clock clk: renesas: r8a7796: Add CANFD clock clk: renesas: r8a7796: Add CAN peripheral clock
2017-01-16clk: samsung: Remove Exynos4415 driver (SoC not supported anymore)Krzysztof Kozlowski4-1421/+0
Support for Exynos4415 is going away because there are no internal nor external users. Since commit 46dcf0ff0de3 ("ARM: dts: exynos: Remove exynos4415.dtsi"), the platform cannot be instantiated so remove also the drivers. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Kukjin Kim <kgene@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-13dt-bindings: clk: add rockchip,grf property for RK3399Xing Zheng1-0/+6
Add support for rockchip,grf property which is used for GRF muxes on RK3399. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-13clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188Heiko Stuebner1-2/+2
Add the newly added clock ids to the clock entries of the rk3066/rk3188 clock driver. We won't be needing them in the kernel for a bit yet but as they're used in the new u-boot ddr setup code/dts we should make sure the clock ids stay identical and do not differ. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-13clk: rockchip: use rk3288 isp_in clock idsJacob Chen1-1/+1
Reference the newly added isp clock-ids in the clock-tree. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-13Merge branch 'v4.11-shared/clkids' into v4.11-clk/nextHeiko Stuebner2-0/+3
2017-01-13clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188Heiko Stuebner1-0/+2
Add clock ids for the upctl and publ controllers used for ddr control. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-13clk: rockchip: add rk3288 isp_in clock idsJacob Chen1-0/+1
Add clock-ids for the isp block of the rk3288. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-12clk: stm32f4: avoid uninitialized variable accessArnd Bergmann1-5/+7
The failure path in the newly added function tries to free an uninitialized pointer: drivers/clk/clk-stm32f4.c: In function 'stm32f4_rcc_init': drivers/clk/clk-stm32f4.c:1106:4: error: 'gate' may be used uninitialized in this function [-Werror=maybe-uninitialized] I'm adding an initialization to NULL here to make the kfree() succeed, and I'm also rearranging the cleanup so that the same kfree() is used for any error path, making the function slightly more robust against newly introduced bugs in the error handling. Fixes: daf2d117cbca ("clk: stm32f4: Add lcd-tft clock") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09Merge branch 'clk-fixes' into clk-nextStephen Boyd1-7/+7
* clk-fixes: clk/samsung: exynos542x: mark some clocks as critical
2017-01-09clk: cdce925: add support for CDCE913, CDCE937, and CDCE949Akinobu Mita3-34/+100
The CDCE925 is a member of the CDCE(L)9xx programmable clock generator family. There are also CDCE913, CDCE937, CDCE949 which have different number of PLLs and outputs. The clk-cdce925 driver supports only CDCE925 in the family. This adds support for the CDCE913, CDCE937, CDCE949, too. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Mike Looijmans <mike.looijmans@topic.nl> Cc: Michael Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: mdm9615: Add EBI2 clockZoran Markovic2-0/+32
Add definition of EBI2 clock used by MDM9615 NAND controller. Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Zoran Markovic <zmarkovic@sierrawireless.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> [sboyd@codeaurora.org: ebi2_clk halt bit is 24 not 23] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: uniphier: remove unneeded #include <linux/delay.h>Masahiro Yamada1-1/+0
This include was needed to suppress build error when this driver was initially merged because <linux/regmap.h> did not include <linux/delay.h> at that time. (developers' headache across sub-systems) The root cause has been fixed by commit adf08d481b52 ("regmap: include <linux/delay.h> from include/linux/regmap.h"), so this line can be dropped now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: mvebu: adjust AP806 CPU clock frequencies to production chipThomas Petazzoni1-5/+23
This commit adjusts the list of possible "Sample At Reset" values that define the CPU clock frequency of the AP806 (part of Marvell Armada 7K/8K) to the values that have been validated with the production chip. Earlier values were preliminary. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09Merge branch 'clk-hi3660' into clk-nextStephen Boyd5-0/+811
* clk-hi3660: clk: hisilicon: Add clock driver for hi3660 SoC dt-bindings: Document the hi3660 clock bindings
2017-01-09clk: hisilicon: Add clock driver for hi3660 SoCZhangfei Gao4-0/+769
Add clock drivers for hi3660 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> [sboyd@codeaurora.org: Simplify probe with function pointer] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09dt-bindings: Document the hi3660 clock bindingsZhangfei Gao1-0/+42
Add DT bindings documentation for hi3660 SoC clock. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk/samsung: exynos542x: mark some clocks as criticalMarek Szyprowski1-7/+7
Some parent clocks of the Exynos542x clock blocks, which have separate power domains (like DISP, MFC, MSC, GSC, FSYS and G2D) must be always enabled to access any register related to power management unit or devices connected to it. For the time being, until a proper solution based on runtime PM is applied, mark those clocks as critical (instead of ignore unused or even no flags) to prevent disabling them. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> [Exynos5800 Peach Pi Chromebook] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: clk-conf: Do not print error messages if EPROBE_DEFERGeert Uytterhoeven1-6/+9
EPROBE_DEFER is not an error, hence printing an error message like clk: couldn't get clock 0 for /soc/display@feb00000 may confuse the user. Suppress error messages in case of probe deferral to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: scpi: don't add cpufreq device if the scpi dvfs node is disabledSudeep Holla1-6/+8
Currently we add the virtual cpufreq device unconditionally even when the SCPI DVFS clock provider node is disabled. This will cause cpufreq driver to throw errors when it gets initailised on boot/modprobe and also when the CPUs are hot-plugged back in. This patch fixes the issue by adding the virtual cpufreq device only if the SCPI DVFS clock provider is available and registered. Fixes: 9490f01e2471 ("clk: scpi: add support for cpufreq virtual device") Reported-by: Michał Zegan <webczat_200@poczta.onet.pl> Cc: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Michał Zegan <webczat_200@poczta.onet.pl> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: qcom: Add GCC_MSS_RESET supportAvaneesh Kumar Dwivedi2-0/+2
Add support to use reset control framework for resetting MSS with hexagon v56 1.5.0. Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: zte: add audio clocks for zx296718Jun Nie3-0/+275
The audio related clock support is missing from the existing zx296718 clock driver. Let's add it, so that the upstream ZX SPDIF driver can work for HDMI audio support. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> [sboyd@codeaurora.org: Staticize some more structures] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09dt-bindings: zx296718-clk: add compatible for audio clock controllerShawn Guo1-0/+3
It adds the compatible string for zx296718 audio clock controller. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: zx296718: do not panic on failureShawn Guo1-9/+18
Instead of using panic, we should give an error message and return error code when of_clk_add_hw_provider() call fails. Since we have error prompt for failures, the "init over" pr_info output isn't really necessary but becomes a debug noise. So let's clean it up along the way. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: wm831x: fix usleep_range with bad rangeNicholas Mc Guire1-1/+2
The delay here is not in atomic context and does not seem critical with respect to precision, but usleep_range(min,max) with min==max results in giving the timer subsystem no room to optimize uncritical delays. Fix this by setting the range to 2000,3000 us. Fixes: commit f05259a6ffa4 ("clk: wm831x: Add initial WM831x clock driver") Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: imx: pllv3: support fractional multiplier on vf610 PLL1/PLL2Nikita Yushchenko3-2/+102
On vf610, PLL1 and PLL2 have registers to configure fractional part of frequency multiplier. This patch adds support for these registers. This fixes "fast system clock" issue on boards where bootloader sets fractional multiplier for PLL1. Suggested-by: Andrey Smirnov <andrew.smirnov@gmail.com> CC: Chris Healy <cphealy@gmail.com> Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk/axs10x: Clear init field in driver probeJose Abreu1-0/+1
Init field must be cleared in driver probe as this structure is not dinamically allocated. If not, wrong flags can be passed to core. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: Carlos Palminha <palminha@synopsys.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Fixes: 923587aafc2c ("clk/axs10x: Add I2S PLL clock driver") Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/040cc9afdfa0e95ce7a01c406ff427ef7dc0c0fd.1481540717.git.joabreu@synopsys.com
2017-01-09Merge branches 'clk-qcom-rpm8974', 'clk-stm32f4', 'clk-ipq4019' and ↵Stephen Boyd9-42/+1242
'clk-fixes' into clk-next * clk-qcom-rpm8974: clk: qcom: smd-rpmcc: Add msm8974 clocks * clk-stm32f4: clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board clk: stm32f4: Add SAI clocks clk: stm32f4: Add I2S clock clk: stm32f4: Add lcd-tft clock clk: stm32f4: Add post divisor for I2S & SAI PLLs clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards clk: stm32f4: Update DT bindings documentation * clk-ipq4019: clk: qcom: ipq4019: Add the cpu clock frequency change notifier clk: qcom: ipq4019: Add all the frequencies for apss cpu clk: qcom: ipq4019: correct sdcc frequency and parent name clk: qcom: ipq4019: Add the nodes for pcnoc clk: qcom: ipq4019: Add the apss cpu pll divider clock node clk: qcom: ipq4019: remove fixed clocks and add pll clocks * clk-fixes: clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method clk: renesas: mstp: Support 8-bit registers for r7s72100
2017-01-06clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFERDouglas Anderson1-1/+0
When we used to defer setting the "grf" member to rockchip_clk_get_grf() it was important to init the "grf" member to an error value in rockchip_clk_init(). With recent changes, we now set "grf" right in rockchip_clk_init() (two lines below the place where we initted it). That makes the old init useless. Get rid of it. Fixes: 6f339dc2719e ("clk: rockchip: lookup General Register Files in rockchip_clk_init") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-05clk: rockchip: add clock controller for rk3328Elaine Zhang3-0/+914
Add the clock tree definition for the new rk3328 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-18 07:12:33 +0000