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2014-09-25Merge tag 'bcm63138-v4' of http://github.com/brcm/linux into next/socArnd Bergmann10-2/+278
Merge "ARM: BCM: Broadcom BCM63138 support" from Florian Fainelli: This patchset adds very minimal support for the BCM63138 SoC which is a xDSL SoC using a dual Cortex A9 CPU complex. * tag 'bcm63138-v4' of http://github.com/brcm/linux: MAINTAINERS: add entry for the Broadcom BCM63xx ARM SoCs ARM: BCM63XX: add BCM963138DVT Reference platform DTS ARM: BCM63XX: add BCM63138 minimal Device Tree ARM: BCM63XX: add low-level UART debug support ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC Conflicts: arch/arm/Kconfig.debug Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-09-25Merge tag 'renesas-soc5-for-v3.18' of ↵Arnd Bergmann2-1/+2
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Pull "Fifth Round of Renesas ARM Based SoC Soc Updates for v3.18" from Simon Horman: * r8a7740: Fix documentation error copied from elsewhere * r8a7794: Reserve memory for CMA in a manner consistent to other R-Car Gen2 SoCs Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'renesas-soc5-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7740 legacy: Fix copied bug in comment ARM: shmobile: r8a7794: Reserve memory as other R-Car Gen2 SoCs
2014-09-25Merge tag 'pxa3xx-ssp-name' of ↵Arnd Bergmann4-9/+51
https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into next/soc Pull "fix PXA3xx SSP naming issue" from Haojian Zhuang: It's imported by 972a55b62 ASoC: fix pxa-ssp compiling issue under mach-mmp from v3.5 Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'pxa3xx-ssp-name' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux: ARM: pxa3xx: provide specific platform_devices for all ssp ports ARM: pxa: ssp: provide platform_device_id for PXA3xx
2014-09-25Merge tag 'tegra-for-3.18-soc' of ↵Arnd Bergmann5-41/+53
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc Pull "ARM: tegra: core SoC code changes for 3.18" from Stephen Warren: the primary change here gets its address information from DT rather than iomap.h. This removes one more user of iomap.h, and will help allow the code to move to a location that can be shared between arch/arm and arch/arm64. An unused header file was also removed. Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'tegra-for-3.18-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra: remove unused tegra_emc.h ARM: tegra: Initialize flow controller from DT of: Add NVIDIA Tegra flow controller bindings
2014-09-25Merge tag 'zynq-cleanup-for-3.18' of git://git.xilinx.com/linux-xlnx into ↵Arnd Bergmann10-63/+207
next/soc Pull "arm: Xilinx Zynq cleanup patches for v3.18" from Michal Simek: - PM support - Fix L2 useless setting Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'zynq-cleanup-for-3.18' of git://git.xilinx.com/linux-xlnx: ARM: zynq: Remove useless L2C AUX setting ARM: zynq: Rename 'zynq_platform_cpu_die' ARM: zynq: Remove hotplug.c ARM: zynq: Synchronise zynq_cpu_die/kill ARM: zynq: cpuidle: Remove pointless code ARM: zynq: Remove invalidate cache for cpu die ARM: zynq: PM: Enable DDR clock stop ARM: zynq: DT: Add DDRC node Documentation: devicetree: Add binding for Synopsys DDR controller ARM: zynq: PM: Enable A9 internal clock gating feature
2014-09-25ARM: meson: add basic support for MesonX SoCsCarlo Caione5-0/+44
This patch adds the basic machine file for the MesonX SoCs. Only Meson6 is populated. Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-09-25ARM: meson: debug: add debug UART for earlyprintk supportCarlo Caione2-2/+47
Add the UART definitions needed to support earlyprintk for MesonX SoCs on UARTAO. Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-09-25irq: Export handle_fasteoi_irqVincent Stehlé1-0/+1
Export handle_fasteoi_irq to be able to use it in e.g. the Zynq gpio driver since commit 6dd859508336 ("gpio: zynq: Fix IRQ handlers"). This fixes the following link issue: ERROR: "handle_fasteoi_irq" [drivers/gpio/gpio-zynq.ko] undefined! Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: linux-arm-kernel@lists.infradead.org Cc: Vincent Stehle <vincent.stehle@laposte.net> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Linus Walleij <linus.walleij@linaro.org> Link: http://lkml.kernel.org/r/1408663880-29179-1-git-send-email-vincent.stehle@laposte.net Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-09-24Merge tag 'imx-soc-3.18' of ↵Olof Johansson39-1990/+521
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc Merge "ARM: imx: SoC updates for 3.18" from Shawn Guo: The i.MX SoC updates for 3.18: - Add initial devicetree support for i.MX1 - Support GPT per clock source from OSC for i.MX6 - A couple of parent selection corrections for i.MX6SL clock driver - Support more chip revision for i.MX6 - Convert pr_warning to pr_warn - Add exclusive gate clock support - Add BYPASS support for i.MX6 PLL clocks - Update i.MX6 clock tree for audio use case - A couple of VF610 clock driver updates * tag 'imx-soc-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (30 commits) ARM: imx_v6_v7_defconfig updates ARM: imx_v4_v5_defconfig: Select CONFIG_IMX_WEIM arm: mach-imx: Convert pr_warning to pr_warn ARM: imx: source gpt per clk from OSC for system timer ARM: imx: add gpt_3m clk for i.mx6qdl ARM: imx: fix register offset of pll7_usb_host gate clock ARM: clk-imx6sl: refine clock tree for SSI ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver ARM: imx6sx: add BYPASS support for PLL clocks ARM: imx6sl: add BYPASS support for PLL clocks ARM: imx6q: add BYPASS support for PLL clocks ARM: imx: add an exclusive gate clock type ARM: clk-imx6q: refine clock tree for SSI ARM: clk-imx6q: refine clock tree for ASRC ARM: clk-imx6sl: correct the pxp and epdc axi clock selections ARM: clk-imx6q: refine clock tree for ESAI ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks ARM: clk-imx6sl: Remove csi_lcdif_sels[] ARM: imx: clk-vf610: Add USBPHY clocks ARM: imx: add cpufreq support for i.mx6sx ... Signed-off-by: Olof Johansson <olof@lixom.net>
2014-09-24Merge tag 'renesas-soc4-for-v3.18' of ↵Olof Johansson1-3/+0
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Merge "Fourth Round of Renesas ARM Based SoC Soc Updates for v3.18" from Simon Horman: Fourth Round of Renesas ARM Based SoC Soc Updates for v3.18 * r8a7794: Remove unnecessary #ifdef CONFIG_USE_OF * tag 'renesas-soc4-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7794: Remove unnecessary #ifdef CONFIG_USE_OF Signed-off-by: Olof Johansson <olof@lixom.net>
2014-09-24ARM: mediatek: Add earlyprintk support for mt6589Matthias Brugger1-0/+10
Enable low-level debug for Mediatek mt6589 SoC on UART0. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-09-24ARM: hisi: Fix platmcpm compilation when ARMv6 is selectedWei Xu1-0/+2
When compiling with "ARCH=arm" and "allmodconfig", with commit: 9cdc99919a95e8b54c1998b65bb1bfdabd47d27b [2/7] ARM: hisi: enable MCPM implementation we will get: /tmp/cc6DjYjT.s: Assembler messages: /tmp/cc6DjYjT.s:63: Error: selected processor does not support ARM mode `ubfx r1,r0,#8,#8' /tmp/cc6DjYjT.s:761: Error: selected processor does not support ARM mode `isb ' /tmp/cc6DjYjT.s:762: Error: selected processor does not support ARM mode `dsb ' /tmp/cc6DjYjT.s:769: Error: selected processor does not support ARM mode `isb ' /tmp/cc6DjYjT.s:775: Error: selected processor does not support ARM mode `isb ' /tmp/cc6DjYjT.s:776: Error: selected processor does not support ARM mode `dsb ' /tmp/cc6DjYjT.s:795: Error: selected processor does not support ARM mode `isb ' /tmp/cc6DjYjT.s:801: Error: selected processor does not support ARM mode `isb ' /tmp/cc6DjYjT.s:802: Error: selected processor does not support ARM mode `dsb ' Fix platmcpm compilation when ARMv6 is selected. Signed-off-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-09-23ARM: debug: fix alphanumerical order on debug uartsOlof Johansson1-10/+10
HIP04 was added out of order, but so was the previous HISI debug uart support as well. Minor reshuffling of order. Signed-off-by: Olof Johansson <olof@lixom.net>
2014-09-23Merge tag 'D01-for-3.18' of git://github.com/hisilicon/linux-hisi into next/socOlof Johansson13-0/+766
Merge "pull request for hisilicon hip04 soc and D01 board updates" from Wei Xu: ARM: mach-hisi: Hisilicon hip04 soc and D01 board updates for 3.18 - Add the CONFIG_MCPM_QUAD_CLUSTER configuration to enlarge cluster number from 2 to 4 - Enable MCPM on HiP04 SoC - Enable 16 cores on HiP04 SoC - Add platform & Fabric controller devicetree binding document for HiP04 SoC - Add hip04.dtsi & hip04-d01.dts for hip04 SoC platform and D01 board - Enable HiP04 SoC in both hi3xxx_defconfig & multi_v7_defconfig - Add the support of Hisilicon HiP04 debug uart * tag 'D01-for-3.18' of git://github.com/hisilicon/linux-hisi: ARM: debug: add HiP04 debug uart ARM: config: enable hisilicon hip04 ARM: dts: add hip04 dts document: dt: add the binding on HiP04 ARM: hisi: enable HiP04 ARM: hisi: enable MCPM implementation ARM: mcpm: support 4 clusters Signed-off-by: Olof Johansson <olof@lixom.net>
2014-09-23Merge tag 'renesas-clk2-for-v3.18' of ↵Olof Johansson1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Merge "Second Round of Renesas ARM Based SoC Clk Updates for v3.18" from Simon Horman. * Add r8a7740, sh73a0 SoCs to MSTP bindings * tag 'renesas-clk2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: clk: shmobile: Add r8a7740, sh73a0 SoCs to MSTP bindings Signed-off-by: Olof Johansson <olof@lixom.net>
2014-09-23Merge tag 'soc-for-v3.18' of ↵Olof Johansson590-2837/+5982
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc SoC related changes for omaps for v3.18 merge window: - PM changes to make the code easier to use on newer SoCs - PM changes for newer SoCs suspend and resume and wake-up events - Minor clean-up to remove dead Kconfig options Note that these have a dependency to the fixes-v3.18-not-urgent tag and is based on a commit in that series. * tag 'soc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (514 commits) ARM: OMAP5+: Reuse OMAP4 PM code for OMAP5 and DRA7 ARM: dts: OMAP3+: Add PRM interrupt ARM: omap: Remove stray ARCH_HAS_OPP references ARM: DRA7: Add hook in SoC initcalls to enable pm initialization ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization ARM: OMAP5 / DRA7: Enable CPU RET on suspend ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug ARM: OMAP5 / DRA7: PM: Avoid all SAR saves ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency ARM: OMAP5 / DRA7: PM: Update CPU context register offset ARM: AM437x: use pdata quirks for pinctrl information ARM: DRA7: use pdata quirks for pinctrl information ARM: OMAP5: use pdata quirks for pinctrl information ARM: OMAP4+: PM: Use only valid low power state for CPU hotplug ARM: OMAP4+: PM: use only valid low power state for suspend ARM: OMAP4+: PM: Make logic state programmable ARM: OMAP2+: powerdomain: introduce logic for finding valid power domain ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdms ...
2014-09-19ARM: pxa3xx: provide specific platform_devices for all ssp portsDaniel Mack3-9/+50
Currently, devices for SSP ports 1, 2 and 3 are registered as compatible devices to pxa27x-ssp. While the actual IP core is comparable, there are some subtle differences which users of the SSP ports address by looking at the 'type' field. By registering devices of type 'pxa27x-ssp', this 'type' field is incorrectly set to PXA27x_SSP which confuses the users. To fix this, provide specific ssp port plaform devices which use 'pxa3xx-ssp' as driver name, an instantiate them from pxa3xx.c. Signed-off-by: Daniel Mack <zonque@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-09-19ARM: pxa: ssp: provide platform_device_id for PXA3xxDaniel Mack1-0/+1
Provide an explicit match string for PXA3xx SSP ports. Without this match string, SSP0/SSP1/SSP2 in PXA3xxx will be consided as PXA27x SSP Port. Signed-off-by: Daniel Mack <zonque@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-09-17MAINTAINERS: add entry for the Broadcom BCM63xx ARM SoCsFlorian Fainelli1-0/+8
Add a MAINTAINERS entry covering all the Broadcom BCM63xx ARM DSL SoCs files along with the relevant git tree and mailing-list. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2014-09-17ARM: BCM63XX: add BCM963138DVT Reference platform DTSFlorian Fainelli2-0/+31
Add a DTS file for the Broadcom BCM963138DVT reference platform board which leverages the bcm63138.dtsi SoC DTSi file. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2014-09-17ARM: BCM63XX: add BCM63138 minimal Device TreeFlorian Fainelli1-0/+134
Add a very minimalistic BCM63138 Device Tree include file which describes the BCM63138 SoC with only the basic set of required peripherals: - Cortex A9 CPUs - ARM GIC - ARM SCU - PL310 Level-2 cache controller - ARM TWD & Global timers - ARM TWD watchdog - legacy MIPS bus (UBUS) - BCM6345-style UARTs (disabled by default) Since the PL310 L2 cache controller does not come out of reset with correct default values, we need to override the 'cache-sets' and 'cache-size' properties to get its geometry right. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2014-09-17ARM: BCM63XX: add low-level UART debug supportFlorian Fainelli2-2/+49
Broadcom BCM63xx DSL SoCs have a different UART implementation for which we need specially crafted low-level debug assembly code to support. Add support for this using the standard definitions provided in include/linux/serial_bcm63xx.h (shared with their MIPS counterparts). Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2014-09-17ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoCFlorian Fainelli4-0/+56
This patch adds basic support for the Broadcom BCM63138 DSL SoC which is using a dual-core Cortex A9 system. Add the very minimum required code boot Linux on this SoC. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2014-09-17ARM: shmobile: r8a7740 legacy: Fix copied bug in commentGeert Uytterhoeven1-1/+1
The corresponding bug in pm-sh7372.c was fixed in commit 70fe7b24672a988f ("ARM: shmobile: Do not access sh7372 A4S domain internals directly"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-09-16ARM: zynq: Remove useless L2C AUX settingMichal Simek1-2/+2
AUX setting has no effect that's why remove it. Warning log: L2C: platform provided aux values match the hardware, so have no effect. Please remove them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-09-16ARM: zynq: Rename 'zynq_platform_cpu_die'Soren Brinkmann1-5/+7
Match the naming pattern of all other SMP ops and rename zynq_platform_cpu_die --> zynq_cpu_die. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-09-16ARM: zynq: Remove hotplug.cSoren Brinkmann4-21/+18
The hotplug code contains only a single function, which is an SMP function. Move that to platsmp.c where all other SMP runctions reside. That allows removing hotplug.c and declaring the cpu_die function static. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-09-16ARM: zynq: Synchronise zynq_cpu_die/killSoren Brinkmann4-1/+52
Avoid races and add synchronisation between the arch specific kill and die routines. The same synchronisation issue was fixed on IMX platform by this commit: "ARM: imx: fix sync issue between imx_cpu_die and imx_cpu_kill" (sha1: 2f3edfd7e27ad4206acbc2ae99c9df5f46353024) Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-09-16ARM: zynq: cpuidle: Remove pointless codeDaniel Lezcano1-9/+1
The core is not powered down, it is pointless to call the cpu_pm notifiers and switch to the global timer. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-and-tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-09-16ARM: zynq: Remove invalidate cache for cpu dieDaniel Lezcano1-31/+1
As there is no Power management unit on this board, it is not possible to power down a core, just WFI is allowed. There is no point to invalidate the cache and exit coherency. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-and-tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-09-16ARM: zynq: PM: Enable DDR clock stopSoren Brinkmann4-1/+87
The DDR controller can detect idle periods and leverage low power features clock stop. When new requests occur, the DDRC resumes normal operation. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-09-16ARM: zynq: DT: Add DDRC nodeSoren Brinkmann1-0/+5
Add the DDR controller to the Zynq devicetree. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-09-16Documentation: devicetree: Add binding for Synopsys DDR controllerSoren Brinkmann1-0/+11
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-09-16ARM: zynq: PM: Enable A9 internal clock gating featureSoren Brinkmann3-0/+30
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-09-16ARM: shmobile: r8a7794: Reserve memory as other R-Car Gen2 SoCsMagnus Damm1-0/+1
Other R-Car Gen2 SoCs such as r8a7790 and r8a7791 reserve the top 256 MiB of memory for use with CMA. Adjust the board-less r8a7794 code to do the same. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-09-16ARM: imx_v6_v7_defconfig updatesFabio Estevam1-6/+4
The rtc isl1208 driver is used by mx6 nitrogen board, so let's enable it by default. The fsl sai driver is used by the vf610-twr board, so let's enable it by default. simple-audio-card driver is used by the vf610-twr board, so let's enable it by default. Generated this patch by doing: - make imx_v6_v7_defconfig - make menuconfig and manually select options - make savedefconfig - cp defconfig arch/arm/configs/imx_v6_v7_defconfig ,which results in some additional cleanups. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16ARM: imx_v4_v5_defconfig: Select CONFIG_IMX_WEIMFabio Estevam1-9/+2
The imx weim driver is used by some mx27/mx1 boards, so let's enable it by default. Generated this patch by doing: - make imx_v4_v5_defconfig - make menuconfig and manually select CONFIG_IMX_WEIM - make savedefconfig - cp defconfig arch/arm/configs/imx_v4_v5_defconfig ,which results in some additional cleanups. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16arm: mach-imx: Convert pr_warning to pr_warnJoe Perches4-6/+6
Use the more common pr_warn. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16ARM: imx: source gpt per clk from OSC for system timerAnson Huang1-5/+26
On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock can be from OSC instead of ipg_per, as ipg_per's rate may be scaled when system enter low bus mode, to keep system timer NOT drift, better to make gpt per clock at fixed rate, here add support for gpt per clock to be from OSC which is at fixed rate always. There are some difference on this implementation of gpt per clock source, see below for details: i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock of OSC / 8 for gpt per clk; i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC for gpt per clk, and we must enable GPT_CR_24MEM to enable OSC clk source for gpt per, GPT_PR_PRESCALER24M is for pre-scaling of this OSC clk, here set it to 8 to make gpt per clk is 3MHz; i.MX6SL: ipg_per can be from OSC directly, so no need to implement this new clk source for gpt per. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16ARM: imx: add gpt_3m clk for i.mx6qdlAnson Huang2-1/+10
Add gpt_3m clock for i.mx6qdl, as gpt can source clock from OSC, some i.MX6 series SOCs has fixed divider of 8 for gpt clock, so here add a fix clk of gpt_3m. i.MX6Q TO1.0 has no gpt_3m option, so force it to be from ipg_per. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16ARM: imx: fix register offset of pll7_usb_host gate clockShawn Guo3-3/+3
There is a copy&paste error on register offset of pll7_usb_host gate clock introduced by i.MX6 PLL bypass support patches. The error breaks the ENET function, because it overwrites the pll6_enet gate bit. Correct the offset for all i.MX6 clock drivers. Thanks to Fugang Duan <B38611@freescale.com> for spotting the error. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16ARM: clk-imx6sl: refine clock tree for SSIShengjiu Wang2-4/+14
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driverShawn Guo1-37/+0
Since ENABLE and BYPASS bits of PLLs are now implemented as separate gate and mux clocks by clock drivers, the code handling these two bits can be removed from clk-pllv3 driver. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16ARM: imx6sx: add BYPASS support for PLL clocksShawn Guo2-10/+78
This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS support for PLL clocks" for imx6q. The difference is that only anaclk1 is available on imx6sx. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16ARM: imx6sl: add BYPASS support for PLL clocksShawn Guo2-9/+87
This is the same change for imx6sl clock driver as "ARM: imx6q: add BYPASS support for PLL clocks" for imx6q. The difference is that only anaclk1 is available on imx6sl. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16ARM: imx6q: add BYPASS support for PLL clocksShawn Guo2-11/+83
The imx6q clock driver currently hard-codes all PLL clocks to source from OSC24M without BYPASS support. The patch adds the missing lvds_in clock which is mutually exclusive with lvds_gate, and implements BYPASS and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits are implemented as mux clocks, and ENABLE bit of PLL clocks is implemented as a gate clock after BYPASS mux. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16ARM: imx: add an exclusive gate clock typeShawn Guo3-1/+99
There are a couple of gate clocks are mutually exclusive on i.MX6, i.e. LVDSCLK1_IBEN and LVDSCLK1_OBEN. They cannot be enabled simultaneously. This patches adds an exclusive gate clock type specifically for such case. The clock driver will need to call imx_clk_gate_exclusive() to register a gate clock with parameter exclusive_mask indicating the mask of gate bits which are mutually exclusive to this gate clock. Right now, it only handles the exclusive gate clocks which are defined in a single hardware register, which is the case we're running into today. But it can be extended to handle exclusive gate clocks defined in different registers later if needed. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16ARM: clk-imx6q: refine clock tree for SSIShengjiu Wang1-3/+9
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16ARM: clk-imx6q: refine clock tree for ASRCShengjiu Wang2-2/+7
ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share the same gate bits. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16ARM: clk-imx6sl: correct the pxp and epdc axi clock selectionsFancy Fang1-3/+4
The parent clocks of IMX6SL_CLK_PXP_AXI_SEL and IMX6SL_CLK_EPDC_AXI_SEL clocks are not the same. So split the epdc_pxp_sels into two different clock selections 'pxp_axi_sels' and 'epdc_axi_sels'. Signed-off-by: Fancy Fang <chen.fang@freescale.com> Signed-off-by: Robby Cai <R63905@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-19 16:10:45 +0000