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2014-03-19clk: at91: replace prog clk round_rate with determine_rateBoris BREZILLON1-28/+28
Implement the determine_rate callback to choose the best parent clk that fulfills the requested rate. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19Documentation: clk: Add locking documentationLaurent Pinchart1-0/+34
Briefly document the common clock framework locking scheme from a clock driver point of view. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19Merge tag 'clk-hisi' of ↵Mike Turquette7-39/+164
https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilcon updating clock drivers for Hisilicon
2014-03-19clk: sunxi: fix thinko in commentEmilio López1-1/+1
This should read MOD0 and not MMC; MMC is just one example of a MOD0 clock. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19clk: sunxi: fix some calculationsEmilio López1-3/+3
Some divisor calculations were misrounded, causing higher than requested rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one homebrew instance of it as well with the right macro. Reported-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19clk: sunxi: fix A20 PLL4 calculationEmilio López1-0/+7
Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19Merge tag 'sunxi-clk-for-3.15' of https://bitbucket.org/emiliolopez/linux ↵Mike Turquette2-48/+344
into clk-next-sunxi Allwinner sunXi SoCs clock changes This adds support for the new, more correct clock node naming and gets the A10 compatibles in line with the rest of the other SoCs. It also adds support for the USB, GMAC and A31's PLL6 clocks. Some of these changes also require DT modifications that will be merged via arm-soc.
2014-03-19clk: hisi: remove static variableHaojian Zhuang4-42/+72
Remove the static variable. So these common clock register helper could be used in more SoCs. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-19clk: hip04: add clock driverHaojian Zhuang4-1/+94
Now only fixed rate clocks are appended into the clock driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-19clk: hisi: assign missing clk to tableHaojian Zhuang1-0/+2
The fixed rate and fixed factor clock isn't registered to clk table. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-18clk: socfpga: Fix section mismatch warningDinh Nguyen1-1/+1
WARNING: drivers/clk/socfpga/built-in.o(.data+0xc0): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_pll_init() The variable socfpga_child_clocks references the function __init socfpga_pll_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x184): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_periph_init() The variable socfpga_child_clocks references the function __init socfpga_periph_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x248): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_gate_init() The variable socfpga_child_clocks references the function __init socfpga_gate_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Reported-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-18Merge tag 'clk-mvebu-3xx-3.15-2' of git://git.infradead.org/linux-mvebu into ↵Mike Turquette2-2/+28
clk-next-mvebu clock: mvebu new SoC changes for v3.15 (incremental pull #2) - mvebu (Armada 375) - fix ratio register offest - mvebu (Armada 380) - expand core divider clock driver to support 380 SoC (enables nand support)
2014-03-18clk: clk-s2mps11: Add support for clocks in S5M8767 MFDTushar Behera2-2/+9
Since clock operation within S2MPS11 and S5M8767 are similar, we can support both the devices within a single driver. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-18clk: clk-s2mps11: Refactor for including support for other MFD clocksTushar Behera1-4/+16
The clocks in S2MPS11 and S5M8767 are managed in the same way, baring a difference in the register offset. It would be better to update existing S2MPS11 driver to support the clocks in S5M8767, rather than creating an almost duplicate driver altogether. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-18clk: add MOXA ART SoCs clock driverJonas Jensen3-0/+146
MOXA ART SoCs allow to determine PLL output and APB frequencies by reading registers holding multiplier and divisor information. Add a clock driver for this SoC. Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-13clk: mvebu: Update binding documentation for the core divider clockEzequiel Garcia1-1/+4
The Core Divider clock support two new compatible strings for Armada 375 and Armada 380 SoCs. Add the compatible strings to the documentation. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-7-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-03-13clk: mvebu: Support Armada 380 SoC on the core divider clockEzequiel Garcia1-0/+23
This commit adds support for the Core Divider clocks of the Armada 380 SoCs. Similarly to Armada 370 and XP, the Core Divider clocks of the 380 have gate capabilities. The only difference is the register layout. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-03-13clk: mvebu: Fix ratio register offset on A375 SoCEzequiel Garcia1-1/+1
This commit fixes the ratio register offset which is 0x4, as per the Armada 375 SoC specification. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394638901-13368-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-26Merge branch 'clk-fixes' into clk-nextMike Turquette2-1/+4
2014-02-26clk: ti/divider: fix rate calculation for fractional ratesTomi Valkeinen1-4/+4
ti/clk-divider.c does not calculate the rates consistently at the moment. As an example, on OMAP3 we have a clock divider with a source clock of 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are: 6: 144000000 7: 123428571.428571... 8: 108000000 Calling clk_round_rate() with the rate in the first column will give the rate in the second column: 144000000 -> 144000000 143999999 -> 123428571 123428572 -> 123428571 123428571 -> 108000000 Note how clk_round_rate() returns 123428571 for rates from 123428572 to 143999999, which is mathematically correct, but when clk_round_rate() is called with 123428571, the returned value is surprisingly 108000000. This means that the following code works a bit oddly: rate = clk_round_rate(clk, 123428572); clk_set_rate(clk, rate); As clk_set_rate() also does clock rate rounding, the result is that the clock is set to the rate of 108000000, not 123428571 returned by the clk_round_rate. This patch changes the ti/clk-divider.c to use DIV_ROUND_UP when calculating the rate. This gives the following behavior which fixes the inconsistency: 144000000 -> 144000000 143999999 -> 123428572 123428572 -> 123428572 123428571 -> 108000000 Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26clk: divider: fix rate calculation for fractional ratesTomi Valkeinen1-5/+5
clk-divider.c does not calculate the rates consistently at the moment. As an example, on OMAP3 we have a clock divider with a source clock of 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are: 6: 144000000 7: 123428571.428571... 8: 108000000 Calling clk_round_rate() with the rate in the first column will give the rate in the second column: 144000000 -> 144000000 143999999 -> 123428571 123428572 -> 123428571 123428571 -> 108000000 Note how clk_round_rate() returns 123428571 for rates from 123428572 to 143999999, which is mathematically correct, but when clk_round_rate() is called with 123428571, the returned value is surprisingly 108000000. This means that the following code works a bit oddly: rate = clk_round_rate(clk, 123428572); clk_set_rate(clk, rate); As clk_set_rate() also does clock rate rounding, the result is that the clock is set to the rate of 108000000, not 123428571 returned by the clk_round_rate. This patch changes the clk-divider.c to use DIV_ROUND_UP when calculating the rate. This gives the following behavior which fixes the inconsistency: 144000000 -> 144000000 143999999 -> 123428572 123428572 -> 123428572 123428571 -> 108000000 Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26clk:at91: Fix memory leak in of_at91_clk_master_setup()Masanari Iida1-1/+1
cppcheck detected following error [clk-master.c:245]: (error) Memory leak: characteristics The original code forgot to free characteristics when irq_of_parse_and_map() failed. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Acked-by Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26clk: axi-clkgen: Add support for v2Lars-Peter Clausen2-44/+270
This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-26clk: hisilicon: add hi3620_mmc_clksZhangfei Gao4-0/+294
Suggest by Arnd: abstract mmc tuning as clock behavior, also because different soc have different tuning method and registers. hi3620_mmc_clks is added to handle mmc clock specifically on hi3620. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26clk: socfpga: Support multiple parents for the pll clocksDinh Nguyen1-4/+22
The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk. Update the clock driver to be able to get the correct parent. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26clk: socfpga: Fix integer overflow in clock calculationDinh Nguyen1-3/+5
Use 64-bit integer for calculating clock rate. Also use do_div for the 64-bit division. Signed-off-by: Graham Moore <grmoore@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26clk: nomadik: fix multiplatform problemLinus Walleij1-0/+3
The Nomadik debugfs screws up multiplatform boots if debugfs is enabled on the multiplatform image, since it's a simple initcall that is unconditionally executed and reads from certain memory locations. Fix this by checking that the driver has been properly initialized, so a base offset to the Nomadik SRC controller exists, before proceeding to register debugfs files. Reported-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-25clk: zynq: Use clk_readl/clk_writel helper functionMichal Simek2-11/+11
Do not use readl/writel directly because the whole clk subsystem is using clk_readl/clk_writel functions. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-25clk: shmobile: div6: use proper description in kernel docWolfram Sang1-1/+1
These variable clocks have nothing to do with MSTP gating, probably a copy&paste leftover. Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-24Merge branch 'clk-fixes' into clk-nextMike Turquette391-2289/+3592
2014-02-24clk: ti: am335x: remove unecessary cpu0 clk nodeNishanth Menon1-1/+0
cpu0 clock node has no functionality, since cpufreq-cpu0 is already capable of picking up the clock from dts. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-24Merge branch 'clocks/fixes/drivers' of git://linuxtv.org/pinchartl/fbdev ↵Mike Turquette375-2197/+3482
into clk-fixes
2014-02-24clk: Correct handling of NULL clk in __clk_{get, put}Sylwester Nawrocki1-6/+7
Ensure clk->kref is dereferenced only when clk is not NULL. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-24clk: return probe defer when DT clock not yet readyJean-Francois Moine2-1/+3
At probe time, a clock device may not be ready when some other device wants to use it. This patch lets the functions clk_get/devm_clk_get return a probe defer when the clock is defined in the DT but not yet available. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-24clk: add pr_debug & kerneldoc around clk notifiersMike Turquette2-1/+18
Both the pr_err and the additional kerneldoc aim to help when debugging errors thrown from within a clock rate-change notifier callback. Reported-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-24Merge branch 'clk-tegra-more-fixes-3.14' of ↵Mike Turquette8-33/+47
git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes Fixes stray access to undefined registers, use of wrong clock parents & running clocks at wrong rates. All of these issues cause regressions in the form of boards that are unable to boot or crash and die horrible deaths.
2014-02-24clk: shmobile: Fix typo in MSTP clock DT bindingsLaurent Pinchart1-2/+2
The DT bindings document a renesas,indices property, while the code, the DT example and the DT sources all use renesas,clock-indices. Fix the documentation. The shmobile mstp DT bindings have been merged in v3.14-rc1 with a bug in the DT ABI, a fix during the -rc series is appropriate. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Simon Horman <horms@verge.net.au>
2014-02-24clk: shmobile: rcar-gen2: Fix qspi divisorLaurent Pinchart1-1/+1
The qspi clock divisor is incorrectly set to twice the value it should have, possibly because it has been computed based on PLL1 as the clock parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal frequencies, not the divisor values). Fix it. This bug introduced in v3.14-rc1 breaks various devices on the Lager and Kolesh shmobile boards and should thus be considered as a regression for which a fix during the -rc series is appropriate. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
2014-02-24clk: shmobile: rcar-gen2: Fix clock parent for all non-PLL clocksLaurent Pinchart1-1/+9
The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as their parent, not the main clock. Fix it. This bug introduced in v3.14-rc1 breaks various devices on the Lager and Kolesh shmobile boards and should thus be considered as a regression for which a fix during the -rc series is appropriate. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
2014-02-23Linux 3.14-rc4v3.14-rc4Linus Torvalds1-1/+1
2014-02-23Merge tag 'fixes-for-linus' of ↵Linus Torvalds26-48/+108
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "A collection of fixes for ARM platforms. Most are fixes for DTS files, mostly from DT conversion on OMAP which is still finding a few issues here and there. There's a couple of small stale code removal patches that we usually queue for the next release instead, but they seemed harmless enough to bring in now. Also, a fix for backlight on some PXA platforms, and a cache configuration fix for Tegra, etc" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (25 commits) MAINTAINERS: add additional ARM BCM281xx/BCM11xxx maintainer ARM: tegra: only run PL310 init on systems with one ARM: tegra: Add head numbers to display controllers ARM: imx6: build pm-imx6q.c independently of CONFIG_PM ARM: tegra: fix RTC0 alias for Cardhu ARM: dove: dt: revert PMU interrupt controller node Documentation: dt: OMAP: Update Overo/Tobi ARM: dts: Add support for both OMAP35xx and OMAP36xx Overo/Tobi ARM: dts: omap3-tobi: Use the correct vendor prefix ARM: dts: omap3-tobi: Fix boot with OMAP36xx-based Overo ARM: OMAP2+: Remove legacy macros for zoom platforms ARM: OMAP2+: Remove MACH_NOKIA_N800 ARM: dts: N900: add missing compatible property ARM: dts: N9/N950: fix boot hang with 3.14-rc1 ARM: OMAP1: nokia770: enable tahvo-usb ARM: OMAP2+: gpmc: fix: DT ONENAND child nodes not probed when MTD_ONENAND is built as module ARM: OMAP2+: gpmc: fix: DT NAND child nodes not probed when MTD_NAND is built as module ARM: dts: omap3-gta04: Fix mmc1 properties. ARM: dts: omap3-gta04: Fix 'aux' gpio key flags. ARM: OMAP2+: add missing ARCH_HAS_OPP ...
2014-02-23Merge tag 'regulator-v3.14-rc4' of ↵Linus Torvalds4-5/+10
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator Pull regulator fixes from Mark Brown: "Mostly unexciting driver fixes, plus one fix to lower the severity of the log message when we don't use an optional regulator - the fixes for ACPI system made this come up more often and it was correctly observed that it was causing undue concern for users" * tag 'regulator-v3.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator: regulator: max14577: Fix invalid return value on DT parse success regulator: core: Change dummy supplies error message to a warning regulator: s5m8767: Add missing of_node_put regulator: s5m8767: Use of_get_child_by_name regulator: da9063: Bug fix when setting max voltage on LDOs 5-11
2014-02-23Merge tag 'clk-mvebu-3xx-3.15' of git://git.infradead.org/linux-mvebu into ↵Mike Turquette7-35/+536
clk-next-mvebu clock: mvebu new SoC changes for v3.15 - mvebu (Armada 375/380/385) - extend corediv clock driver to support new SoCs - add core and gating clock drivers for new SoCs
2014-02-23clk: ux500: Staticize ux500_twocell_getSachin Kamat1-1/+2
ux500_twocell_get is a local symbol. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-23clk: tegra: Staticize tegra_clk_periph_no_gate_opsSachin Kamat1-1/+1
tegra_clk_periph_no_gate_ops is a local symbol. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-23Merge branch 'timers-urgent-for-linus' of ↵Linus Torvalds1-17/+29
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer fix from Thomas Gleixner: "Serialize the registration of a new sched_clock in the currently ARM only generic sched_clock facilty to avoid sched_clock havoc" * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: sched_clock: Prevent callers from seeing half-updated data
2014-02-23Merge branch 'x86-urgent-for-linus' of ↵Linus Torvalds3-21/+18
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Thomas Gleixner: - a bugfix which prevents a divide by 0 panic when the newly introduced try_msr_calibrate_tsc() fails - enablement of the Baytrail platform to utilize the newfangled msr based calibration * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86: tsc: Add missing Baytrail frequency to the table x86, tsc: Fallback to normal calibration if fast MSR calibration fails
2014-02-23Merge branch 'irq-urgent-for-linus' of ↵Linus Torvalds1-3/+19
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Thomas Gleixner: "Another four fixlets to tame the ARM orion irq chip" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip: orion: Fix getting generic chip pointer. irqchip: orion: clear stale interrupts in irq_startup irqchip: orion: use handle_edge_irq on bridge irqs irqchip: orion: clear bridge cause register on init
2014-02-23clk: add clock-indices supportBen Dooks2-1/+36
Add a property called clock-indices to allow clock-output-names to be used where the index used to lookup a clock is not a 1:1 mapping to the array position in the clock-output-names Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-23Merge tag 'usb-3.14-rc4' of ↵Linus Torvalds19-111/+159
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB fixes from Greg KH: "Here are a number of USB fixes for reported issues for 3.14-rc4 The majority of these are for USB gadget, phy, and musb driver issues. And there's a few new device ids thrown in for good measure" * tag 'usb-3.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: usb: chipidea: need to mask when writting endptflush and endptprime usb: musb: correct use of schedule_delayed_work() usb: phy: msm: fix compilation errors when !CONFIG_PM_SLEEP usb: gadget: fix NULL pointer dereference usb: gadget: printer: using gadget_is_otg to check otg support at runtime phy: let phy_provider_register be the last step in registering PHY phy-core: Don't allow building phy-core as a module phy-core: Don't propagate -ENOSUPP from phy_pm_runtime_get_sync to caller phy-core: phy_get: Leave error logging to the caller phy,phy-bcm-kona-usb2.c: Add dependency on HAS_IOMEM usb: musb: correct use of schedule_delayed_work() usb: musb: do not sleep in atomic context USB: serial: option: blacklist interface 4 for Cinterion PHS8 and PXS8 USB: EHCI: add delay during suspend to prevent erroneous wakeups usb: gadget: bcm63xx_udc: fix build failure on DMA channel code usb: musb: do not sleep in atomic context usb: gadget: s3c2410_udc: Fix build error usb: musb: core: Fix remote-wakeup resume usb: musb: host: Fix SuperSpeed hub enumeration usb: musb: fix obex in g_nokia.ko causing kernel panic
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-09 02:35:32 +0000