diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/haswellx/other.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/haswellx/other.json | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/other.json b/tools/perf/pmu-events/arch/x86/haswellx/other.json new file mode 100644 index 000000000000..4e1b6ce96ca3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswellx/other.json @@ -0,0 +1,43 @@ +[ + { + "EventCode": "0x5C", + "UMask": "0x1", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING0", + "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5C", + "UMask": "0x2", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "EventCode": "0x5C", + "UMask": "0x1", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING0_TRANS", + "CounterMask": "1", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x63", + "UMask": "0x1", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", + "Counter": "0,1,2,3", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
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